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SAA7105E/V1/S1,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70
2004 Mar 04 55
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
10 THERMAL CHARACTERISTICS
Note
1. The overall R
th(j-a)
value can vary depending on the board layout. To minimize the effective R
th(j-a)
all power and
ground pins must be connected to the power and ground layers directly. An ample copper area direct under the
SAA7104E; SAA7105E with a number of through-hole plating, which connect to the ground layer (four-layer board:
second layer), can also reduce the effective R
th(j-a)
. Please do not use any solder-stop varnish under the chip. In
addition the usage of soldering glue with a high thermal conductance after curing is recommended.
11 CHARACTERISTICS
T
amb
= 0 to 70 °C (typical values excluded); unless otherwise specified.
SYMBOL PARAMETER CONDITIONS VALUE UNIT
R
th(j-a)
thermal resistance from junction to ambient in free air 38
(1)
K/W
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
V
DDA
analog supply voltage 3.15 3.3 3.45 V
V
DDD2
,
V
DDD3
,
V
DDD4
digital supply voltage 3.15 3.3 3.45 V
V
DDD1
digital supply voltage (DVO) 1.045 1.1 1.155 V
1.425 1.5 1.575 V
1.71 1.8 1.89 V
2.375 2.5 2.625 V
3.135 3.3 3.465 V
I
DDA
analog supply current note 1 1 110 115 mA
I
DDD
digital supply current note 2 1 175 200 mA
Inputs
V
IL
LOW-level input voltage V
DDD1
= 1.1 V, 1.5 V, 1.8 V
or 2.5 V; note 3
−0.1 − +0.2 V
V
DDD1
= 3.3 V; note 3 −0.5 − +0.8 V
pins RESET, TMS, TCK,
TRST and TDI
−0.5 − +0.8 V
V
IH
HIGH-level input voltage V
DDD1
= 1.1 V, 1.5 V, 1.8 V
or 2.5 V; note 3
V
DDD1
− 0.2 − V
DDD1
+ 0.1 V
V
DDD1
= 3.3 V; note 3 2 − V
DDD1
+ 0.3 V
pins RESET, TMS, TCK,
TRST and TDI
2 − V
DDD2
+ 0.3 V
I
LI
input leakage current −−10 µA
C
i
input capacitance clocks −−10 pF
data −−10 pF
I/Os at high-impedance −−10 pF
2004 Mar 04 56
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Outputs
V
OL
LOW-level output voltage V
DDD1
= 1.1 V, 1.5 V, 1.8 V
or 2.5 V; note 3
0 − 0.1 V
V
DDD1
= 3.3 V; note 3 0 − 0.4 V
pins TDO,
TTXRQ_XCLKO2, VSM
and HSM_CSYNC
0 − 0.4 V
V
OH
HIGH-level output voltage V
DDD1
= 1.1 V, 1.5 V, 1.8 V
or 2.5 V; note 3
V
DDD1
− 0.1 − V
DDD1
V
V
DDD1
= 3.3 V; note 3 2.4 − V
DDD1
V
pins TDO,
TTXRQ_XCLKO2, VSM
and HSM_CSYNC
2.4 − V
DDD2
V
I
2
C-bus; pins SDA and SCL
V
IL
LOW-level input voltage −0.5 − 0.3V
DDD2
V
V
IH
HIGH-level input voltage 0.7V
DDD2
− V
DDD2
+ 0.3 V
I
i
input current V
i
= LOW or HIGH −10 − +10 µA
V
OL
LOW-level output voltage
(pin SDA)
I
OL
=3mA −−0.4 V
I
o
output current during acknowledge 3 −− mA
Clock timing; pins PIXCLKI and PIXCLKO
T
PIXCLK
cycle time note 4 12 −− ns
t
d(CLKD)
delay from PIXCLKO to
PIXCLKI
note 5 −−−ns
δ duty factor t
HIGH
/T
PIXCLK
note 4 40 50 60 %
duty factor t
HIGH
/T
CLKO2
output 40 50 60 %
t
r
rise time note 4 −−1.5 ns
t
f
fall time note 4 −−1.5 ns
Input timing
t
SU;DAT
input data set-up time pins PD11 to PD0 2 −− ns
t
HD;DAT
input data hold time pins PD11 to PD0 0.9 −− ns
t
SU;DAT
input data set-up time pins HSVGC, VSVGC
and FSVGC; note 6
2 −− ns
t
HD;DAT
input data hold time pins HSVGC, VSVGC
and FSVGC; note 6
1.5 −− ns
Crystal oscillator
f
nom
nominal frequency − 27 − MHz
∆f/f
nom
permissible deviation of
nominal frequency
note 7 −50 − +50 10
−6
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2004 Mar 04 57
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
CRYSTAL SPECIFICATION
T
amb
ambient temperature 0 − 70 °C
C
L
load capacitance 8 −− pF
R
S
series resistance −−80 Ω
C
1
motional capacitance (typical) 1.2 1.5 1.8 fF
C
0
parallel capacitance (typical) 2.8 3.5 4.2 pF
Data and reference signal output timing
C
o(L)
output load capacitance 8 − 40 pF
t
o(h)(gfx)
output hold time to graphics
controller
pins HSVGC, VSVGC,
FSVGC and CBO
1.5 −− ns
t
o(d)(gfx)
output delay time to graphics
controller
pins HSVGC, VSVGC,
FSVGC and CBO
−−10 ns
t
o(h)
output hold time pins TDO,
TTXRQ_XCLKO2, VSM
and HSM_CSYNC
3 −− ns
t
o(d)
output delay time pins TDO,
TTXRQ_XCLKO2, VSM
and HSM_CSYNC
−−25 ns
CVBS and RGB outputs
V
o(CVBS)(p-p)
output voltage CVBS
(peak-to-peak value)
see Table 117 − 1.23 − V
V
o(VBS)(p-p)
output voltage VBS (S-video)
(peak-to-peak value)
see Table 117 − 1 − V
V
o(C)(p-p)
output voltage C (S-video)
(peak-to-peak value)
see Table 117 − 0.89 − V
V
o(RGB)(p-p)
output voltage R, G, B
(peak-to-peak value)
see Table 117 − 0.7 − V
∆V
o
inequality of output signal
voltages
− 2 − %
R
o(L)
output load resistance − 37.5 −Ω
B
DAC
output signal bandwidth of
DACs
−3 dB; note 8 − 170 − MHz
ILE
lf(DAC)
low frequency integral linearity
error of DACs
−−±3 LSB
DLE
lf(DAC)
low frequency differential
linearity error of DACs
−−±1 LSB
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70

SAA7105E/V1/S1,557

Mfr. #:
Buy SAA7105E/V1/S1,557
Manufacturer:
NXP Semiconductors
Description:
IC DIGITAL VIDEO ENCODER 156LBGA
Lifecycle:
New from this manufacturer.
Delivery:
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