2004 Mar 04 37
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Table 49 Subaddresses 63H to 66H (four bytes to program subcarrier frequency)
Note
1. Examples:
a) NTSC M: f
fsc
= 227.5, f
llc
= 1716 → FSC = 569408543 (21F07C1FH).
b) PAL B/G: f
fsc
= 283.7516, f
llc
= 1728 → FSC = 705268427 (2A098ACBH).
Table 50 Subaddresses 67H to 6AH
Table 51 Subaddresses 6CH and 6DH
Table 52 Subaddress 6DH
Table 53 Subaddress 6EH
DATA BYTE DESCRIPTION CONDITIONS REMARKS
FSC0 to FSC3 f
fsc
= subcarrier frequency (in multiples
of line frequency); f
llc
= clock frequency
(in multiples of line frequency)
;
note 1
FSC3 = most significant byte;
FSC0 = least significant byte
DATA BYTE DESCRIPTION REMARKS
L21O0 first byte of captioning data, odd field LSBs of the respective bytes are encoded immediately
after run-in and framing code, the MSBs of the respective
bytes have to carry the parity bit, in accordance with the
definition of line 21 encoding format.
L21O1 second byte of captioning data, odd field
L21E0 first byte of extended data, even field
L21E1 second byte of extended data, even field
DATA BYTE DESCRIPTION
HTRIG sets the horizontal trigger phase related to chip-internal horizontal input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases
delays of all internally generated timing signals; the default value is 0
DATA BYTE DESCRIPTION
VTRIG sets the vertical trigger phase related to chip-internal vertical input
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG = 0 to 31 (1FH); the default value is 0
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
NVTRIG 0 values of the VTRIG register are positive
1 values of the VTRIG register are negative
BLCKON 0 encoder in normal operation mode; default after reset
1 output signal is forced to blanking level
PHRES − selects the phase reset mode of the colour subcarrier generator; see Table 54
LDEL − selects the delay on luminance path with reference to chrominance path; see Table 55
FLC − field length control; see Table 56
FSC round
f
fsc
f
llc
--------
2
32
×
=
