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SAA7105E/V1/S1,557

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70
2004 Mar 04 40
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Table 64 Subaddresses 78H, 79H and 7CH
Table 65 Subaddresses 7AH to 7CH
Table 66 Subaddress 7CH
Table 67 Subaddresses 7EH and 7FH
Table 68 Subaddresses 81H to 83H
DATA BYTE DESCRIPTION REMARKS
TTXEVS first line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0) in even field
TTXEVS = 04H; is default
after reset if strapped to PAL
TTXEVS = 05H; is default
after reset if strapped to
NTSC
line = (TTXEVS + 4) for M-systems
line = (TTXEVS + 1) for other systems
TTXEVE last line of occurrence of signal TTXRQ on pin TTXRQ_XCLKO2
(CLK2EN = 0) in even field
TTXEVE = 16H; is default
after reset if strapped to PAL
TTXEVE = 10H; is default
after reset if strapped to
NTSC
line = (TTXEVE + 3) for M-systems
line = TTXEVE for other systems
DATA BYTE DESCRIPTION
FAL first active line = FAL + 4 for M-systems and FAL + 1 for other systems, measured in lines
FAL = 0 coincides with the first field synchronization pulse
LAL last active line = LAL + 3 for M-systems and LAL for other system, measured in lines
LAL = 0 coincides with the first field synchronization pulse
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
TTX60 0 enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset
1 enables world standard teletext 60 Hz (FISE = 1)
TTXO 0 new teletext protocol selected; at each rising edge of TTXRQ a single teletext bit is
requested (see Fig.14); default after reset
1 old teletext protocol selected; the encoder provides a window of TTXRQ going HIGH; the
length of the window depends on the chosen teletext standard (see Fig.14)
DATA BYTE DESCRIPTION
LINE individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective
bits, disabled line = LINExx (50 Hz field rate)
this bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE
DATA BYTE DESCRIPTION
PCL defines the frequency of the synthesized pixel clock PIXCLKO;
; f
XTAL
= 27 MHz nominal, e.g. 640 × 480 to NTSC M: PCL = 20F63BH;
640 × 480 to PAL B/G: PCL = 1B5A73H (as by strapping pins)
f
PIXCLK
PCL
2
24
-----------
f
XTAL
×


8×=
2004 Mar 04 41
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Table 69 Subaddress 84H
Table 70 Logic levels and function of PCLE
Table 71 Logic levels and function of PCLI
Table 72 Subaddress 85H
Table 73 Subaddresses 90H and 94H
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
DCLK − set to logic 1 (default after reset is logic 0)
PCLSY 0 pixel clock generator runs free; default after reset
1 pixel clock generator gets synchronized with the vertical sync
IFRA 0 input FIFO gets reset explicitly at falling edge
1 input FIFO gets reset every field; default after reset
IFBP 0 input FIFO is active
1 input FIFO is bypassed; default after reset
PCLE − controls the divider for the external pixel clock; see Table 70
PCLI − controls the divider for the internal pixel clock; see Table 71
DATA BYTE
DESCRIPTION
PCLE1 PCLE0
0 0 divider ratio for PIXCLK output is 1
0 1 divider ratio for PIXCLK output is 2; default after reset
1 0 divider ratio for PIXCLK output is 4
1 1 divider ratio for PIXCLK output is 8
DATA BYTE
DESCRIPTION
PCLI1 PCLI0
0 0 divider ratio for internal PIXCLK is 1
0 1 divider ratio for internal PIXCLK is 2; default after reset
1 0 divider ratio for internal PIXCLK is 4
1 1 not allowed
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
EIDIV 0 set to logic 0 if DVO compliant signals are applied; default after reset
1 set to logic 1 if non-DVO compliant signals are applied
FILI − threshold for FIFO internal transfers; nominal value is 8; default after reset
DATA BYTE DESCRIPTION
XOFS horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite
blanking (CBO) output
2004 Mar 04 42
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Table 74 Subaddresses 91H and 94H
Table 75 Subaddresses 92H and 94H
Table 76 Subaddresses 93H and 94H
Table 77 Subaddresses 95H and 96H
Table 78 Subaddress 96H
DATA BYTE DESCRIPTION
XPIX pixel in X direction; defines half the number of active pixels per input line (identical to the length of
CBO pulses)
DATA BYTE DESCRIPTION
YOFSO vertical offset in odd field; defines (in the odd field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSO + 2; usually,
YOFSO = YOFSE with the exception of extreme vertical downscaling and interlacing
DATA BYTE DESCRIPTION
YOFSE vertical offset in even field; defines (in the even field) the number of lines from VSVGC to first line with
active CBO; if no LUT data is requested, the first active CBO will be output at YOFSE + 2; usually,
YOFSE = YOFSO with the exception of extreme vertical downscaling and interlacing
DATA BYTE DESCRIPTION
YPIX defines the number of requested input lines from the feeding device;
number of requested lines = YPIX + YOFSE − YOFSO
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
EFS 0 frame sync signal at pin FSVGC ignored in slave mode
1 frame sync signal at pin FSVGC accepted in slave mode
PCBN 0 normal polarity of CBO signal (HIGH during active video)
1 inverted polarity of CBO signal (LOW during active video)
SLAVE 0 the SAA7104E; SAA7105E is timing master to the graphics controller
1 the SAA7104E; SAA7105E is timing slave to the graphics controller
ILC 0 if hardware cursor insertion is active, set LOW for non-interlaced input signals
1 if hardware cursor insertion is active, set HIGH for interlaced input signals
YFIL 0 luminance sharpness booster disabled
1 luminance sharpness booster enabled
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P70

SAA7105E/V1/S1,557

Mfr. #:
Buy SAA7105E/V1/S1,557
Manufacturer:
NXP Semiconductors
Description:
IC DIGITAL VIDEO ENCODER 156LBGA
Lifecycle:
New from this manufacturer.
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