2004 Mar 04 43
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Table 79 Subaddress 97H
Table 80 Subaddresses 98H and 99H
Table 81 Subaddress 99H
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
HFS 0 horizontal sync is directly derived from input signal (slave mode) at pin HSVGC
1 horizontal sync is derived from a frame sync signal (slave mode) at pin FSVGC (only if
EFS is set HIGH)
VFS 0 vertical sync (field sync) is directly derived from input signal (slave mode) at
pin VSVGC
1 vertical sync (field sync) is derived from a frame sync signal (slave mode) at
pin FSVGC (only if EFS is set HIGH)
OFS 0 pin FSVGC is switched to input
1 pin FSVGC is switched to active output
PFS 0 polarity of signal at pin FSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
1 polarity of signal at pin FSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
OVS 0 pin VSVGC is switched to input
1 pin VSVGC is switched to active output
PVS 0 polarity of signal at pin VSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
1 polarity of signal at pin VSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
OHS 0 pin HSVGC is switched to input
1 pin HSVGC is switched to active output
PHS 0 polarity of signal at pin HSVGC in output mode (master mode) is active HIGH; rising
edge of the input signal is used in slave mode
1 polarity of signal at pin HSVGC in output mode (master mode) is active LOW; falling
edge of the input signal is used in slave mode
DATA BYTE DESCRIPTION
HLEN
horizontal length;
DATA BYTE DESCRIPTION
IDEL input delay; defines the distance in PIXCLKs between the active edge of
CBO and the first received
valid pixel
HLEN
number of PIXCLKs
line
-----------------------------------------------------
1=
2004 Mar 04 44
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Table 82 Subaddresses 9AH and 9CH
Table 83 Subaddresses 9BH and 9CH
Table 84 Subaddresses 9DH and 9FH
Table 85 Subaddresses 9EH and 9FH
Table 86 Subaddresses A0H and A1H
Table 87 Subaddress A1H
Table 88 Subaddresses A2H to A4H
DATA BYTE DESCRIPTION
XINC
incremental fraction of the horizontal scaling engine;
DATA BYTE DESCRIPTION
YINC
incremental fraction of the vertical scaling engine;
DATA BYTE DESCRIPTION
YIWGTO
weighting factor for the first line of the odd field;
DATA BYTE DESCRIPTION
YIWGTE
weighting factor for the first line of the even field;
DATA BYTE DESCRIPTION
YSKIP vertical line skip; defines the effectiveness of the anti-flicker filter; YSKIP = 0: most effective;
YSKIP = 4095: anti-flicker filter switched off
DATA BYTE
LOGIC
LEVEL
DESCRIPTION
BLEN 0 no internal blanking for non-interlaced graphics in bypass mode; default after reset
1 forced internal blanking for non-interlaced graphics in bypass mode
DATA BYTE DESCRIPTION
BCY, BCU
and BCV
luminance and colour difference portion of border colour in underscan area
XINC
number of output pixels
line
--------------------------------------------------------------
number of input pixels
line
----------------------------------------------------------
--------------------------------------------------------------
4096×=
YINC
number of active output lines
number of active input lines
----------------------------------------------------------------------------
4096×=
YIWGTO
YINC
2
--------------
2048+=
YIWGTE
YINC YSKIP
2
--------------------------------------
=
2004 Mar 04 45
Philips Semiconductors Product specification
Digital video encoder SAA7104E; SAA7105E
Table 89 Subaddress D0H
Table 90 Layout of the data bytes in the line count array
Table 91 Subaddress D1H
Table 92 Layout of the data bytes in the line type array
Table 93 Subaddress D2H
DATA BYTE DESCRIPTION
HLCA RAM start address for the HD sync line count array; the byte following subaddress D0 points to the
first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing
until stop condition. Each line count array entry consists of 2 bytes; see Table 90. The array has
15 entries.
HLC HD line counter. The system will repeat the pattern described in ‘HLT’ HLC times and then start with
the next entry in line count array.
HLT HD line type pointer. If not 0, the value points into the line type array, index HLT 1 with the
description of the current line. 0 means the entry is not used.
BYTE DESCRIPTION
0 HLC7 HLC6 HLC5 HLC4 HLC3 HLC2 HLC1 HLC0
1 HLT3 HLT2 HLT1 HLT0 0 0 HLC9 HLC8
DATA BYTE DESCRIPTION
HLTA RAM start address for the HD sync line type array; the byte following subaddress D1 points to the first
cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing
until stop condition. Each line type array entry consists of 4 bytes; see Table 92. The array has
15 entries.
HLP HD line type; if not 0, the value points into the line pattern array. The index used is HLP 1. It consists
of value-duration pairs. Each entry consists of 8 pointers, used from index 0 to 7. The value 0 means
that the entry is not used.
BYTE DESCRIPTION
0 0 HLP12 HLP11 HLP10 0 HLP02 HLP01 HLP00
1 0 HLP32 HLP31 HLP30 0 HLP22 HLP21 HLP20
2 0 HLP52 HLP51 HLP50 0 HLP42 HLP41 HLP40
3 0 HLP72 HLP71 HLP70 0 HLP62 HLP61 HLP60
DATA BYTE DESCRIPTION
HLPA RAM start address for the HD sync line pattern array; the byte following subaddress D2 points to the
first cell to be loaded with the next transmitted byte; succeeding cells are loaded by auto-incrementing
until stop condition. Each line pattern array entry consists of 4 value-duration pairs occupying 2 bytes;
see Table 94. The array has 7 entries.
HPD HD pattern duration. The value defines the time in pixel clocks (HPD + 1) the corresponding value
HPV is added to the HD output signal. If 0, this entry will be skipped.
HPV HD pattern value pointer. This gives the index in the HD value array containing the level to be inserted
into the HD output path. If the MSB of HPV is logic 1, the value will only be inserted into the Y/GREEN
channel of the HD data path, the other channels remain unchanged.

SAA7105E/V1/S1,557

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC DIGITAL VIDEO ENCODER 156LBGA
Lifecycle:
New from this manufacturer.
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