PCA8561 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 27 March 2015 26 of 55
NXP Semiconductors
PCA8561
Automotive 18 × 4 LCD segment driver
11.1.2 START and STOP conditions
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 19
).
11.1.3 Acknowledge
Each byte of 8 bits is followed by an acknowledge cycle. An acknowledge is defined as
logic 0. A not-acknowledge is defined as logic 1.
When written to, the slave will generate an acknowledge after the reception of each byte.
After the acknowledge, another byte may be transmitted. It is also possible to send a
STOP or START condition.
When read from, the master receiver must generate an acknowledge after the reception
of each byte. When the master receiver no longer requires bytes to be transmitted, it must
generate a not-acknowledge. After the not-acknowledge, either a STOP or START
condition must be sent.
Remark: The PCA8561 omits the not-acknowledge. After the last byte read, the end of
transmission is indicated by a STOP or START condition from the master.
A detailed description of the I
2
C-bus specification is given in Ref. 12 “UM10204”.
11.1.4 I
2
C interface protocol
The PCA8561 uses the I
2
C interface for data transfer. Interpretation of the data is
determined by the interface protocol.
11.1.4.1 Write protocol
After the I
2
C slave address is transmitted, the PCA8561 requires that the register address
pointer is defined. It can take the value 00h to 0Fh. Values outside of that range will result
in the transfer being ignored, however the slave will still respond with acknowledge
pulses.
After the register address has been transmitted, write data is transmitted. The minimum
number of data write bytes is 0 and the maximum number is unlimited. After each write,
the address pointer increments by one. After address 0Fh, the address pointer stops
incrementing at address 10h.
• I
2
C START condition
• I
2
C slave address + write
• start register pointer
• write data
• write data
• :
• write data
• I
2
C STOP condition; an I
2
C RE-START condition is also possible.
