NCV8855
http://onsemi.com
3
PIN FUNCTION DESCRIPTIONS
Pin No. Symbol Description
5 SYS_EN Main enable pin for the IC. A logic high on this pin will enable the part. Leaving this pin floating or driving it to
ground will place the IC in shutdown mode.
6 LDO_EN Enable pin for both LDO controllers. A logic high on this pin will enable both LDO controllers. If this pin is left
floating, an internal pull down keeps the LDOs disabled.
7 HS_EN Enable pin for the high−side load switch. A logic high on this pin will enable the HSS. If this pin is left floating,
an internal pull down keeps the HSS disabled.
8 HOT_FLG Thermal warning indicator. This pin provides an early warning signal of an impending thermal shutdown.
22 DRV_VPP
Output of the internal 7.2 V linear regulator. Bypass this pin with 1 mF to ground.
35 5V_IC
Output of the internal 5 V linear regulator. Bypass this pin with 0.1 mF to ground.
36 DRAIL
Output of the internal 4.2 V linear regulator. Bypass this pin with 0.1 mF to ground.
4 SYNC Synchronization pin. Use this pin to synchronize the internal oscillator to an external clock. If synchronization
is not used, connect this pin to AGND.
37 AGND Analog ground. Reference point for internal signals.
SWITCH−MODE POWER SUPPLY 1 (SMPS1) PIN CONNECTIONS
27
OCSET Overcurrent set pin, used to set the current limit threshold. A resistor connected from this pin and the upper
MOSFET Drain sets the current limit protection level.
29 SW_FB1 Output voltage feedback pin. Connect a resistor divider network to VOUT1 to set the desired output voltage.
30 COMP1
This pin is the output of the error amplifier and the non-inverting input of the PWM comparator. Use
this pin in conjunction with the SW_FB1 pin to compensate the voltage-mode control feedback
loop.
25 BST1 This pin is the supply rail for the upper N−Channel MOSFET. An internal bootstrap diode brings DRV_VPP to
this pin. Connect a ceramic capacitor (C
BST1
) between this pin and the SN1 pin. A typical value for C
BST1
is
0.1 mF.
24 GH1 GH1 is the output pin of the internal upper N−Channel MOSFET gate driver. Keep the trace from this pin to
the gate of the upper MOSFET as short as possible to achieve the best turn−on and turn−off performance
and to reduce electro−magnetic emissions.
23 SN1 This pin is the return path of the upper floating gate driver. Connect this pin to the source of the upper
MOSFET. This pin is also used to sense the current flowing through the upper MOSFETs.
21 GL1 GL1 is the output pin of the synchronous rectifier gate driver. Connect this pin to the lower N−channel
MOSFET.
20 PGND This pin is the return path for SMPS1 lower MOSFET driver current. Connect this pin to the source of the
lower MOSFET.
PINS NOT INTERNALLY CONNECTED TO SILICON
EP
− Exposed pad of QFN package. Connect to printed circuit board ground to improve thermal performance.
12 thru
19
These pins can be left floating or tied to ground to improve thermal performance.
SWITCH−MODE POWER SUPPLY 2 (SMPS2) PIN CONNECTIONS
10
VIN_SW This pin is the supply rail for the internal upper N−Channel MOSFET. Bypass this pin with a local ceramic
capacitor. Additional bulk capacitance may be required based off output requirements. Refer to application
section for more information.
3 SW_FB2 Output voltage feedback pin. Connect a resistor divider network to VOUT2 to set the desired output voltage.
2 COMP2 This pin is the output of the error amplifier and the non−inverting input of the PWM comparator. Use this pin
in conjunction with the SW_FB2 pin to compensate the voltage−controlled feedback loop.
11 BST2 This pin is the supply rail for the internal upper N−Channel MOSFET. An internal bootstrap diode brings
DRV_VPP to this pin. Connect a ceramic capacitor (C
BST2
) between this pin and the SN2 pin. A typical value
for C
BST2
is 0.1 mF.
9 SN2 Source output of the internal upper N−channel MOSFET.
