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19
SMPS2 Diode Selection
The diode in SMPS2 provides the inductor current path
when the power switch turns off. This is known as the
nonsynchronous diode or commutation diode. The peak
reverse voltage is equal to the maximum operating input
voltage. The peak conducting current is determined by the
internal current limit. The average current can be calculated
from:
I
D(avg)
+ IOUT2
ǒ
1 *
VOUT2
VIN_SW
Ǔ
(eq. 10)
However, the worse case diode average current occurs
during a short circuit condition. For a diode to survive an
indefinite short circuit condition, the current rating of the
diode should be equal to the maximum current limit which
is 3.6 A. Thus the MBRS4201T3 is the diode of choice.
Inductor Selection
Both mechanical and electrical considerations influence
the selection of an output inductor. From a mechanical
perspective, smaller inductor values generally correspond to
smaller physical size. Since the inductor is often one of the
largest components in SMPS system, a minimum inductor
value is particularly important in spaceconstrained
applications. From an electrical perspective, smaller
inductor values correspond to faster transient response. The
maximum current slew rate through the output inductor for
a buck regulator is given by:
Inductor Slew Rate +
dI
L
dt
+
V
L
L
(eq. 11)
Where I
L
is the inductor current, L is the output
inductance, and V
L
is the voltage drop across the inductor.
This equation indicates that larger inductor values limit the
regulators ability to slew current through the output
inductor in response to output load transients. Consequently,
output capacitors must supply (or store) sufficient charge to
maintain regulation while the inductor current “catches up”
to the load. This results in larger values of output capacitance
to maintain tight output voltage regulation.
In contrast, smaller values of inductance increase the
regulators maximum achievable slew rate and decrease the
necessary capacitance, at the expense of higher ripple
current.
In continuous conduction mode, the peaktopeak ripple
current is calculated using the following equation:
I
PP
+ FSW
VOUT
L
ǒ
1 *
VOUT
VBATT
Ǔ
(eq. 12)
From this equation it is clear that the ripple current
increases as L decreases, emphasizing the tradeoff between
dynamic response and ripple current.
For most applications, the inductor value falls in the range
between 2.2 mH and 22 mH. There are many magnetic
component vendors providing standard product
lines suitable for SMPS1 and SMPS2’s requirements.
TDK offers the RLF12545PF series inductors, which are
recommended for the automotive radio application.
SMPS Output Capacitor Selection
The output capacitor is a basic component for the fast
response of the power supply. In fact, during load transient,
for first few microseconds they supply the current to the
load. The controller recognizes the load transient and
proceeds to increase the duty cycle to its maximum.
Neglecting the effect of the ESL, the output voltage has a
first drop due to the ESR of the bulk capacitor(s).
DVOUT
ǒ
ESR
Ǔ
+ DIOUT ESR
(eq. 13)
A lower ESR produces a lower DV during load transient.
In addition, a lower ESR produces a lower output voltage
ripple.
The voltage drop due to the output capacitor discharge can
be approximated using the following equation:
DVOUT
ǒ
discharge
Ǔ
+
(
DIOUT
)
2
L
2 COUT
ǒ
VIN
ǒ
min
Ǔ
D
MAX
* VOUT
Ǔ
(eq. 14)
where, D
MAX
is the maximum duty cycle value, which is
90%. Although the ESR effect is not in phase with the
discharging of the output voltage, DVOUT
(ESR)
can be
added to DVOUT
(discharge)
to give a rough indication of the
maximum DVOUT during a transient condition. Simulation
can also help determine the maximum DVOUT; however, it
will ultimately have to be verified with the actual load since
the ESL effect is dependent on layout and the actual load’s
di/dt.
SMPS Input Capacitor Selection
The primary consideration for selecting the input
capacitor is input RMS current. However, since there are
two SMPS running outofphase with each other,
calculating the input RMS current can be complicated. The
graphs below shows how the input RMS current is affected
by differing phase angles between SMPS1 and SMPS2. The
plot below was generated with VOUT1 at 5 V with a load of
2 A and an output inductor value of 10 mH, and VOUT2 at
8 V with a load of 4 A and an output inductor value of 10 mH.
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
0.00 60.00 120.00 180.00 240.00 300.00 360.00
Phase (VOUT1 vs VOUT2)
Irms
9.00
10.00
11.00
12.00
13.00
14.00
15.00
16.00
17.00
18.00
Figure 22. Irms vs Phase
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1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
0.00% 20.00% 40.00% 60.00% 80.00% 100.00%
Clock Duty cycle
Irms
9.00
10.00
11.00
12.00
13.00
14.00
15.00
16.00
17.00
18.00
Figure 23. Irms vs Phase
Here it is shown that the “sweet spot” phase angle (where
the input RMS current is the lowest) happens at the same
location (in terms of phase relationship) regardless of input
voltage. Thus, once the output voltages are known, a sweet
spot can be determined. After determining the sweet spot,
the input capacitors can be chosen accordingly to handle the
RMS current.
The purpose of interleaving the two SMPS is to eliminate
any overlapping of there input currents. This will reduce the
overall input RMS current. Since the outputs are running at
different voltages, they will have different duty cycles, and
thus running with 180° phase difference does not necessarily
guarantee an optimal input RMS current reduction. The
figures below describe, graphically, this point.
50%
Duty cycle clock
2T
8V delayed by
180deg or 1/2T
Input current
Overlap
T
5V
Figure 24.
Since the 8 V rail has a wider pulse, with a 50% internal
clock duty cycle, there will be some amount of input current
overlapping which will produce a less than ideal RMS
current. The following figure shows an optimized duty cycle
where there is no overlapping.
2T
8 V delayed by
144deg or 2/5T
Input current
No input current
Overlap
T
40%
Duty cycle clock
5V
Figure 25.
To achieve this optimization, the SYNC function on the
NCV8855 will have to be used with a 40% duty cycle clock.
However, when looking at the worstcase input RMS
(which occurs at high battery) a 40% duty cycle clock will
yield the same input RMS current as a 50% duty cycle clock.
Thus, the only true benefit of this optimization occurs when
a narrow input voltage range is assured. Therefore, a 50%
duty cycle clock is always recommended.
SMPS Compensation
The NCV8855 utilizes voltage mode control. The control
loop regulates V
OUT
by sampling V
OUT
and controlling the
duty cycle. Inherent with all voltagemode control loops is
a compensation network.
V
REF
V
RAMP
ESR
C
OUT
L
OUT
C1
C2
C3
R1
R3R2
V
OUT
V
IN
COMP
FB
EA
PWM
COMPARATOR
DCR
Figure 26.
The compensation network consists in the internal error
amplifier and the impedance networks Z
IN
(R1, R3 and C3)
and Z
FB
(R2, C1 and C2). The compensation network has to
provide a closed loop transfer function with the highest 0 dB
crossing frequency to have fast response and the highest gain
in dc conditions to minimize the load regulation. A stable
NCV8855
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21
control loop has a gain crossing with 20 dB/decade slope
and a phase margin greater than 45°.
Error Amplifier
Closed Loop Gain
Compensation Network
Modulator Gain
w
dB
Figure 27.
w
Z1
+
1
R
2
@ C
2
w
Z2
+
1
ǒ
R
1
) R
3
Ǔ
@ C
3
w
P1
+
1
ǒ
C
1
@C
2
C
1
)C
2
Ǔ
w
P2
+
1
R
3
@ C
3
w
LC
+
1
L
OUT
@ C
OUT
Ǹ
w
ESR
+
1
ESR @ C
OUT
To reiterate, there are 3 primary goals to compensating.
Goal 1 is to have a high a unity gain bandwidth (UGB) that
is greater than 1/10 the switching frequency, but less than 1/2
the switching frequency. UGB is also known as the
crossover frequency. This is the point where the closed loop
gain = 0 dB or a gain of 1. In the plot above, the UGB is the
point where the red line crosses the W axis. Goal 2 is to have
the closed loop gain cross 0 dB with a 20 dB/decade slope
also known as a 1 slope. Goal 3 is to achieve over 45° of
phase margin when the gain crosses 0 dB.
These are just goals. Sometimes the crossover frequency
is reduced below 1/10 FSW in order to meet goal 3.
Conversely, some designs will push the crossover frequency
as high as it can (as long as it is below 1/2 FSW) with a
reduce phase margin of 30° in order to get a faster transient
response. The only two absolutes are that the crossover
frequency cannot exceed 1/2 FSW and the phase margin has
to be greater than 0° at crossover. However, a SMPS
operating towards these absolutes will experience sever
ringing before it dampens out.
To achieve the above goals, the following guidelines
should be adopted.
Place wZ1 at half the resonance of wLC
Place wZ2 at or around wLC
Place wP1 at wESR
Place wP2 at half the switching frequency
Performing these calculations will take some amount of
iterations and bench testing to verify results. However,
ON Semiconductor has developed a tool to speed up the
design process tremendously with great ease and accuracy.
This tool can be downloaded by following the below link.
http://www.onsemi.com/pub/Collateral/COMPCALC.ZIP

NCV8855BMNR2GEVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
BOARD EVALUATION NCV8855 ASIC
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