NCV8855
http://onsemi.com
15
THEORY OF OPERATION
Device Description
The NCV8855 is a multiple output controller / regulator
IC with an integrated high−side load switch. The NCV8855
will address automotive radio system and instrument cluster
power supply requirements. In addition to the high−side
load switch, the NCV8855 comprise a switch−mode power
supply (SMPS) buck controller, a 2 A SMPS buck regulator,
and two low dropout linear regulator controllers (LDO). The
NCV8855 in combination with the ultra−low Iq NCV861x
IC forms an eight output automotive radio or instrument
cluster power solution.
LR_G1
22
8 HOT_FLG
AGND
37
6
5V_IC
5
35
SYS_EN
LDO_EN
DRV_VPP
26
28
VIN
HS_S
HS_EN
7
29SW_FB1
23
21
24GH1
SN1
GL1
25
27OCSET
BST1
30
COMP1
9
BST2
10
11
SN2
3
SW_FB2
2
COMP2
4
SYNC/
ROSC
38LR_FB1
39ISNS1−
40ISNS1+
33
34
LR_G2
LR_FB2
32 ISNS2−
31 ISNS2+
PGND
20
VIN_SW
SMPS1
VOUT1
SMPS2
VOUT2
LDO2
VOUT4
HIGH−SIDE
SWITCH
MAIN
LDO1
VOUT3
Figure 17.
1
The NCV8855 has an internally set switching frequency
of 170 kHz and provides an SYNC pin for external
frequency synchronization. The NCV8855 is designed to
operate within the range of 9 V to 18 V. The switch−mode
power supplies are voltage−mode controlled and the LDO
controllers drive P−channel MOSFETs as pass devices.
System Enable (SYS_EN)
The system enable (SYS_EN) pin is used to start device
operation or place it in low quiescent shutdown. Driving this
pin high will allow the two main internal voltage rails
(DRV_VPP and 5V_IC) to power up. These voltage rails
require external bypassing and have independent UVLO trip
points. Both rails must be operational in order for the IC to
function. After exceeding its UVLO threshold, the IC will
power up the switch−mode power supplies with a soft−start.
Conversely, a logic−low on the pin will power down the
DRV_VPP and 5V_IC rails and place the IC in an ultra−low
current shutdown state.
Linear Regulator Enable (LDO_EN)
The low−dropout linear regulators (LDOs) have a
dedicated enable pin. This pin controls the startup and
shutdown of the LDOs. The SYS_EN pin must be logic high
for this pin to function. It is possible to drive this pin high
coincidentally with SYS_EN, but the LDO outputs will not
startup until DRV_VPP and 5V_IC have increased above its
UVLO thresholds.
High−Side Switch Enable (HS_EN)
The high−side switch enable controls only the high−side
switch. Similar to LDO_EN, the SYS_EN pin must be logic
high for this pin to function. The voltage level on all enable
pins have been designed to work with 3.3 V or 5 V logic.
IC Power (VIN, VIN_SW, DRV_VPP, 5V_IC)
There are many input voltage rails for the NCV8855. The
main power supply input for the IC is VIN. The DRV_VPP,
5V_IC and the high−side switch drain are all driven from
V
IN
. The DRV_VPP voltage rail is the power rail for SMPS1
& SMPS2’s gate driver circuits. The 5V_IC voltage rail is
the main supply for the IC. The VIN_SW rail is the supply
rail for SMPS2’s internal upper MOSFET. VIN_SW is
directly tied to the drain of the N−channel MOSFET.
DRV_VPP
internal
regulator
5V_IC internal
regulator
High−Side
Switch
SMPS1 & 2
Gate Drivers
Main IC
DRV_VPP
5V_IC
LDO1 LDO2
VIN
SMPS2
Internal upper
MOSFET
VIN_SW
ISNS1+
ISNS1−
ISNS2+
ISNS2−
Figure 18.
Two additional inputs rails are ISNS1+ and ISNS2+.
These inputs not only serve as the positive reference for the
current sense circuit, but also serve as the supply rail for the
LDO error amplifier.
Startup and Shutdown Behavior
The startup sequence primary depends on the system
configuration. However, in every case, enable SYS_EN
first. The SYNC pin must not be held at logic high before
SYS_EN is enabled. Below shows typical startup and
