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AD9512UCPZ-EP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
AD9512-EP Enhanced Product
Rev. 0 | Page 16 of 20
Figure 7. LVPECL Differential Output @ 800 MHz
Figure 8. LVDS Differential Output @ 800 MHz
Figure 9. CMOS Single-Ended Output @ 250 MHz with 10 pF Load
Figure 10. LVPECL Differential Output Swing vs. Frequency
Figure 11. LVDS Differential Output Swing vs. Frequency
Figure 12. CMOS Single-Ended Output Swing vs. Frequency and Load
VERT 500mV/DIV HORIZ 500ps/DIV
10463-007
VERT 100mV/DIV HORIZ 500ps/DIV
10463-008
VERT 500mV/DIV HORIZ 1ns/DIV
10463-009
OUTPUT FREQUENCY (MHz)
DIFFERENTIAL SWING (V p-p)
100 16001100600
1.2
1.3
1.4
1.5
1.6
1.7
1.8
10463-010
OUTPUT FREQUENCY (MHz)
DIFFERENTIAL SWING (mV p-p)
100 900700500300
500
750
700
650
600
550
10463-011
OUTPUT FREQUENCY (MHz)
OUTPUT (V
PK
)
0 600500400300200100
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
2pF
10pF
20pF
10463-012
Enhanced Product AD9512-EP
Rev. 0 | Page 17 of 20
Figure 13. Additive Phase Noise—LVPECL DIV1, 245.76 MHz
Distribution Section Only
Figure 14. Additive Phase Noise—LVDS DIV1, 245.76 MHz
Figure 15. Additive Phase Noise—CMOS DIV1, 245.76 MHz
Figure 16. Additive Phase Noise—LVPECL DIV1, 622.08 MHz
Figure 17. Additive Phase Noise—LVDS DIV2, 122.88 MHz
Figure 18. Additive Phase Noise—CMOS DIV4, 61.44 MHz
OFFSET (Hz)
L(f) (dBc/Hz)
10 10M1M100k10k1k100
–170
–110
–130
–120
–140
–150
–160
10463-013
OFFSET (Hz)
L(f) (dBc/Hz)
10 10M1M100k10k1k100
–170
–80
–90
–110
–100
–120
–130
–140
–150
–160
10463-014
OFFSET (Hz)
L(f) (dBc/Hz)
10 10M1M100k10k1k100
–170
–100
–110
–120
–130
–140
–150
–160
10463-015
OFFSET (Hz)
L(f) (dBc/Hz)
10 10M1M100k10k1k100
–170
–110
–130
–120
–140
–150
–160
10463-016
OFFSET (Hz)
L(f) (dBc/Hz)
10 10M1M100k10k1k100
–170
–80
–90
–110
–100
–120
–130
–140
–150
–160
10463-017
OFFSET (Hz)
L(f) (dBc/Hz)
10 10M1M100k10k1k100
–170
–100
–110
–120
–130
–140
–150
–160
10463-018
AD9512-EP Enhanced Product
Rev. 0 | Page 18 of 20
OUTLINE DIMENSIONS
Figure 19. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Range Package Description Package Option
AD9512UCPZ-EP −55°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1
AD9512UCPZ-EP-R7 −55°C to +85°C 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-48-1
1
Z = RoHS Compliant Part.
PIN 1
INDICATOR
TOP
VIEW
6.75
BSC SQ
7.00
BSC SQ
1
48
12
13
37
36
24
25
5.25
5.10 SQ
4.95
0.50
0.40
0.30
0.30
0.23
0.18
0.50 BSC
12° MAX
0.20 REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
5.50
REF
0.05 MAX
0.02 NOM
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
COPLANARITY
0.08
SEATING
PLANE
0.25 MIN
EXPOSED
PAD
(BOTTOM VIEW)
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
080108-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD9512UCPZ-EP

Mfr. #:
Buy AD9512UCPZ-EP
Manufacturer:
Analog Devices Inc.
Description:
Clock Drivers & Distribution 1.2GHz Dividers Delay Adj 5 Outputs
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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