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AD9512UCPZ-EP

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
Enhanced Product AD9512-EP
Rev. 0 | Page 7 of 20
Parameter Min Typ Max Unit Test Conditions/Comments
CLK1 = 245.76 MHz, OUT = 122.88 MHz
Divide Ratio = 2
@ 10 Hz Offset −118 dBc/Hz
@ 100 Hz Offset −127 dBc/Hz
@ 1 kHz Offset −137 dBc/Hz
@ 10 kHz Offset −147 dBc/Hz
@ 100 kHz Offset −154 dBc/Hz
@ 1 MHz Offset
−156
dBc/Hz
>10 MHz Offset −158 dBc/Hz
CLK1-TO-CMOS ADDITIVE PHASE NOISE
CLK1 = 245.76 MHz, OUT = 245.76 MHz
Divide Ratio = 1
@ 10 Hz Offset −110 dBc/Hz
@ 100 Hz Offset −121 dBc/Hz
@ 1 kHz Offset −130 dBc/Hz
@ 10 kHz Offset −140 dBc/Hz
@ 100 kHz Offset
−145
dBc/Hz
@ 1 MHz Offset −149 dBc/Hz
> 10 MHz Offset −156 dBc/Hz
CLK1 = 245.76 MHz, OUT = 61.44 MHz
Divide Ratio = 4
@ 10 Hz Offset −122 dBc/Hz
@ 100 Hz Offset −132 dBc/Hz
@ 1 kHz Offset −143 dBc/Hz
@ 10 kHz Offset −152 dBc/Hz
@ 100 kHz Offset −158 dBc/Hz
@ 1 MHz Offset −160 dBc/Hz
>10 MHz Offset −162 dBc/Hz
CLK1 = 78.6432 MHz, OUT = 78.6432 MHz
Divide Ratio = 1
@ 10 Hz Offset −122 dBc/Hz
@ 100 Hz Offset −132 dBc/Hz
@ 1 kHz Offset −140 dBc/Hz
@ 10 kHz Offset −150 dBc/Hz
@ 100 kHz Offset
−155
dBc/Hz
@ 1 MHz Offset −158 dBc/Hz
>10 MHz Offset −160 dBc/Hz
CLK1 = 78.6432 MHz, OUT = 39.3216 MHz
Divide Ratio = 2
@ 10 Hz Offset −128 dBc/Hz
@ 100 Hz Offset −136 dBc/Hz
@ 1 kHz Offset −146 dBc/Hz
@ 10 kHz Offset −155 dBc/Hz
@ 100 kHz Offset −161 dBc/Hz
>1 MHz Offset −162 dBc/Hz
AD9512-EP Enhanced Product
Rev. 0 | Page 8 of 20
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK1 = 622.08 MHz, 40 fs rms BW = 12 kHz to 20 MHz (OC-12)
Any LVPECL (OUT0 to OUT2) = 622.08 MHz,
Divide Ratio = 1
CLK1 = 622.08 MHz 55 fs rms BW = 12 kHz to 20 MHz (OC-3)
Any LVPECL (OUT0 to OUT2) = 155.52 MHz
Divide Ratio = 4
CLK1 = 400 MHz 215 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
215
fs rms
Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 100 MHz Interferer(s)
Both LVDS (OUT3, OUT4) = 100 MHz Interferer(s)
CLK1 = 400 MHz 222 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz Interferer(s)
Both LVDS (OUT3, OUT4) = 50 MHz
Interferer(s)
CLK1 = 400 MHz 225 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz Interferer(s)
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off)
Interferer(s)
CLK1 = 400 MHz 225 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz Interferer(s)
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On) Interferer(s)
LVDS OUTPUT ADDITIVE TIME JITTER
CLK1 = 400 MHz 264 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz 319 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
LVDS (OUT4) = 50 MHz Interferer(s)
All LVPECL = 50 MHz Interferer(s)
Enhanced Product AD9512-EP
Rev. 0 | Page 9 of 20
Parameter Min Typ Max Unit Test Conditions/Comments
CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
LVDS (OUT3) = 50 MHz Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CLK1 = 400 MHz 367 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CMOS (OUT4) = 50 MHz (B Outputs Off) Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CLK1 = 400 MHz 367 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CMOS (OUT3) = 50 MHz (B Outputs Off) Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CLK1 = 400 MHz 548 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CMOS (OUT4) = 50 MHz (B Outputs On) Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CLK1 = 400 MHz 548 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CMOS (OUT3) = 50 MHz (B Outputs On) Interferer(s)
All LVPECL = 50 MHz Interferer(s)
CMOS OUTPUT ADDITIVE TIME JITTER
CLK1 = 400 MHz 275 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
Both CMOS (OUT3, OUT4) = 100 MHz (B Output On)
Divide Ratio = 4
CLK1 = 400 MHz 400 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz Interferer(s)
LVDS (OUT4) = 50 MHz Interferer(s)
CLK1 = 400 MHz 374 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz Interferer(s)
CMOS (OUT4) = 50 MHz (B Output Off) Interferer(s)
CLK1 = 400 MHz 555 fs rms Calculated from SNR of ADC method;
f
C
= 100 MHz with A
IN
= 170 MHz
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz Interferer(s)
CMOS (OUT4) = 50 MHz (B Output On) Interferer(s)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

AD9512UCPZ-EP

Mfr. #:
Buy AD9512UCPZ-EP
Manufacturer:
Analog Devices Inc.
Description:
Clock Drivers & Distribution 1.2GHz Dividers Delay Adj 5 Outputs
Lifecycle:
New from this manufacturer.
Delivery:
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