DS2780 Standalone Fuel Gauge IC
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Table 3. PARAMETER EEPROM MEMORY BLOCK 1
ADDRESS
(HEX)
DESCRIPTION ADDRESS
(HEX)
DESCRIPTION
60 CONTROL - Control Register 70 AE 3040 Slope
61 AB - Accumulation Bias 71 AE 2030 Slope
62 AC - Aging Capacity MSB 72 AE 1020 Slope
63 AC - Aging Capacity LSB 73 AE 0010 Slope
64 VCHG - Charge Voltage 74 SE 3040 Slope
65 IMIN - Minimum Charge Current 75 SE 2030 Slope
66 VAE - Active Empty Voltage 76 SE 1020 Slope
67 IAE - Active Empty Current 77 SE 0010 Slope
68 Active Empty 40 78 RSGAIN - Sense Resistor Gain MSB
69 RSNSP - Sense Resistor Prime 79 RSGAIN - Sense Resistor Gain LSB
6A Full 40 MSB 7A RSTC - Sense Resistor Temp. Coeff.
6B Full 40 LSB 7B FRSGAIN - Factory Gain MSB
6C Full 3040 Slope 7C FRSGAIN - Factory Gain LSB
6D Full 2030 Slope 7D Reserved
6E Full 1020 Slope 7E Reserved
6F Full 0010 Slope 7F Reserved
1-WIRE BUS SYSTEM
The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-Wire bus
with multiple slaves. A single-drop bus has only one slave device. In all instances, the DS2780 is a slave device.
The bus master is typically a microprocessor in the host system. The discussion of this bus system consists of four
topics: 64-bit net address, hardware configuration, transaction sequence, and 1-Wire signaling.
64-BIT NET ADDRESS
Each DS2780 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first eight bits are
the 1-Wire family code (32h for DS2780). The next 48 bits are a unique serial number. The last eight bits are a
cyclic redundancy check (CRC) of the first 56 bits (see Figure 18). The 64-bit net address and the 1-Wire I/O
circuitry built into the device enable the DS2780 to communicate through the 1-Wire protocol detailed in the 1-Wire
Bus System section of this data sheet.
Figure 18. 1-Wire Net Address Format
8-BIT CRC 48-BIT SERIAL NUMBER
8-BIT FAMILY
CODE (32h)
MSb LSb
CRC GENERATION
The DS2780 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure error-free
transmission of the address, the host system can compute a CRC value from the first 56 bits of the address and
compare it to the CRC from the DS2780. The host system is responsible for verifying the CRC value and taking
action as a result. The DS2780 does not compare CRC values and does not prevent a command sequence from
proceeding as a result of a CRC mismatch. Proper use of the CRC can result in a communication channel with a
very high level of integrity.
The CRC can be generated by the host using a circuit consisting of a shift register and XOR gates as shown in
Figure 19, or it can be generated in software. Additional information about the Dallas 1-Wire CRC is available in
DS2780 Standalone Fuel Gauge IC
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Application Note 27, Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor Touch
Memory Products. (This application note can be found on the Maxim/Dallas Semiconductor website at
www.maxim-ic.com.)
In the circuit in Figure 19, the shift register bits are initialized to 0. Then, starting with the least significant bit of the
family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, then the serial
number is entered. After the 48th bit of the serial number has been entered, the shift register contains the CRC
value.
Figure 19. 1-Wire CRC Generation Block Diagram
HARDWARE CONFIGURATION
Because the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive it at the
appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the bus with open-drain
or tri-state output drivers. The DS2780 uses an open-drain output driver as part of the bidirectional interface
circuitry shown in Figure 20. If a bidirectional pin is not available on the bus master, separate output and input pins
can be connected together.
The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the value of
this resistor should be approximately 5k. The idle state for the 1-Wire bus is high. If, for any reason, a bus
transaction must be suspended, the bus must be left in the idle state to properly resume the transaction later. If the
bus is left low for more than 120s (16s for overdrive speed), slave devices on the bus begin to interpret the low
period as a reset pulse, effectively terminating the transaction.
The DS2780 can operate in two communication speed modes, standard and overdrive. The speed mode is
determined by the input logic level of the OVD pin; a logic 0 selects standard speed and a logic 1 selects overdrive
speed. The OVD pin must be at a stable logic level of 0 or 1 before initializing a transaction with a reset pulse. All
1-Wire devices on a multinode bus must operate at the same communication speed for proper operation. 1-Wire
timing for both standard and overdrive speeds are listed in the Electrical Characteristics: 1-Wire Interface tables.
Figure 20. 1-Wire Bus Interface Circuitry
0.2
A
(typ)
100
MOSFET
TX
RX
Rx
Tx
RX = RECEIVE
TX = TRANSMIT
Vpullup
(2.0V to 5.5V)
4.7k
BUS MASTER DS2780 1-WIRE PORT
MSb
XOR
XOR
LSb
XOR
INPUT
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TRANSACTION SEQUENCE
The protocol for accessing the DS2780 through the 1-Wire port is as follows:
Initialization
Net Address Command
Function Command
Transaction/Data
The sections that follow describe each of these steps in detail.
All transactions of the 1-Wire bus begin with an initialization sequence consisting of a reset pulse transmitted by the
bus master followed by a presence pulse simultaneously transmitted by the DS2780 and any other slaves on the
bus. The presence pulse tells the bus master that one or more devices are on the bus and ready to operate. For
more details, see the 1-Wire Signaling section.
NET ADDRESS COMMANDS
Once the bus master has detected the presence of one or more slaves, it can issue one of the net address
commands described in the following paragraphs. The name of each ROM command is followed by the 8-bit
opcode for that command in square brackets. Figure 21 presents a transaction flowchart of the net address
commands.
Read Net Address [33h or 39h]. This command allows the bus master to read the DS2780’s 1-Wire net address.
This command can only be used if there is a single slave on the bus. If more than one slave is present, a data
collision occurs when all slaves try to transmit at the same time (open drain produces a wired-AND result). The
RNAOP bit in the status register selects the opcode for this command, with RNAOP = 0 indicating 33h, and
RNAOP = 1 indicating 39h.
Match Net Address [55h]. This command allows the bus master to specifically address one DS2780 on the 1-Wire
bus. Only the addressed DS2780 responds to any subsequent function command. All other slave devices ignore
the function command and wait for a reset pulse. This command can be used with one or more slave devices on
the bus.
Skip Net Address [CCh]. This command saves time when there is only one DS2780 on the bus by allowing the
bus master to issue a function command without specifying the address of the slave. If more than one slave device
is present on the bus, a subsequent function command can cause a data collision when all slaves transmit data at
the same time.
Search Net Address [F0h]. This command allows the bus master to use a process of elimination to identify the 1-
Wire net addresses of all slave devices on the bus. The search process involves the repetition of a simple three-
step routine: read a bit, read the complement of the bit, then write the desired value of that bit. The bus master
performs this simple three-step routine on each bit location of the net address. After one complete pass through all
64 bits, the bus master knows the address of one device. The remaining devices can then be identified on
additional iterations of the process. See Chapter 5 of the Book of DS19xx i
Button
®
Standards for a comprehensive
discussion of a net address search, including an actual example. (This publication can be found on the
Maxim/Dallas Semiconductor website at www.maxim-ic.com.)
Resume [A5h]. This command increases data throughput in multidrop environments where the DS2780 needs to
be accessed several times. Resume is similar to the Skip Net Address command in that the 64-bit net address
does not have to be transmitted each time the DS2780 is accessed. After successfully executing a Match Net
Address command or Search Net Address command, an internal flag is set in the DS2780. When the flag is set,
the DS2780 can be repeatedly accessed through the Resume command function. Accessing another device on the
bus clears the flag, thus preventing two or more devices from simultaneously responding to the Resume command
function.
iButton is a registered trademark of Maxim Integrated Products, Inc.

DS2780G+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Battery Management Stand-Alone Fuel Gauge
Lifecycle:
New from this manufacturer.
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