MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
10 ______________________________________________________________________________________
Pin Description (continued)
PIN
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
NAME FUNCTION
10 CH5 Channel 5 Analog Input
11 CH6 Channel 6 Analog Input
12 CH7 Channel 7 Analog Input
13 13 13
INTCLK/
EXTCLK
Clock-Mode Select Input. Use INTCLK/EXTCLK to select the internal
or external conversion clock. Connect INTCLK/EXTCLK to AV
DD
to
select the internal clock. Connect INTCLK/EXTCLK to AGND to use
an external clock connected to CLK.
18 18 18 REF
MS
Midscale Reference Bypass or Input. REF
MS
is the bypass point for
an internally generated reference voltage. For the MAX1316/
MAX1317/MAX1318, connect a 0.1µF capacitor from REF
MS
to
AGND. For the MAX1320/MAX1321/MAX1322/MAX1324/
MAX1325/MAX1326, connect REF
MS
directly to REF and bypass
with a 0.1µF capacitor from REF
MS
to AGND.
19 19 19 REF
ADC Reference Bypass or Input. REF is the bypass point for an
internally generated reference voltage. Bypass REF with a 0.01µF
capacitor to AGND. REF can be driven externally by a precision
external voltage reference.
20 20 20 REF+
Positive Reference Bypass. REF+ is the bypass point for an
internally generated reference voltage. Bypass REF+ with a 0.1µF
capacitor to AGND. Also bypass REF+ to REF- with a 2.2µF and a
0.1µF capacitor.
21 21 21 COM
Reference Common Bypass. COM is the bypass point for an
internally generated reference voltage. Bypass COM to AGND with
a 2.2µF and a 0.1µF capacitor.
22 22 22 REF-
Negative Reference Bypass. REF- is the bypass point for an
internally generated reference voltage. Bypass REF- with a 0.1µF
capacitor to AGND. Also bypass REF- to REF+ with a 2.2µF and a
0.1µF capacitor.
24 24 24 D0
Digital I/O Bit 0 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
25 25 25 D1
Digital I/O Bit 1 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
26 26 26 D2
Digital I/O Bit 2 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
______________________________________________________________________________________ 11
Pin Description (continued)
PIN
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
NAME FUNCTION
27 27 27 D3
Digital I/O Bit 3 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
28 28 28 D4
Digital I/O Bit 4 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
29 29 29 D5
Digital I/O Bit 5 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
30 30 30 D6
Digital I/O Bit 6 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
31 31 31 D7
Digital I/O Bit 7 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
32 32 32 D8
Digital Out Bit 8 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
33 33 33 D9
Digital Out Bit 9 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
34 34 34 D10
Digital Out Bit 10 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
35 35 35 D11
Digital Out Bit 11 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
36 36 36 D12
Digital Out Bit 12 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
37 37 37 D13
Digital Out Bit 13 of 14-Bit Parallel Data Bus. High impedance when
RD = 1 or CS = 1.
38 38 38 DV
DD
Digital-Supply Input. Apply +2.7V to +5.25V to DV
DD
. Bypass DV
DD
to DGND with a 0.1µF capacitor.
39 39 39 DGND
Digital-Supply GND. DGND is the power return for DV
DD
. Connect
DGND to AGND at only one point (see the Layout, Grounding, and
Bypassing section).
40 40 40 EOC
End-of-Conversion Output. EOC goes low to indicate the end of a
conversion. EOC returns high after one clock period.
MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
12 ______________________________________________________________________________________
Pin Description (continued)
PIN
MAX1316
MAX1320
MAX1324
MAX1317
MAX1321
MAX1325
MAX1318
MAX1322
MAX1326
NAME FUNCTION
41 41 41 EOLC
End-of-Last-Conversion Output. EOLC goes low to indicate the end
of the last conversion. EOLC returns high when CONVST goes low
for the next conversion sequence.
42 42 42 RD
Read Input. When RD and CS go low, the device initiates a read
command of the parallel data buses, D0–D13. D0–D13 are high
impedance while either RD or CS is high.
43 43 43 WR
Write Input. The write command initiates when WR and CS go low. A
write command loads the configuration byte on D0–D7.
44 44 44 CS
Chip-Select Input. Pulling CS low activates the digital interface.
D0–D13 are high impedance while either CS or RD is high.
45 45 45 CONVST
Convert-Start Input. Driving CONVST high places the device in hold
mode and initiates the conversion process. The analog inputs are
sampled on the rising edge of CONVST. When CONVST is low, the
analog inputs are tracked.
46 46 46 CLK
External-Clock Input. CLK accepts an external-clock signal up to
15MHz. Connect CLK to DGND for internally clocked conversions.
To select external-clock mode, set INTCLK/EXTCLK = 0.
47 47 47 SHDN
Shutdown Input. Set SHDN = 0 for normal operation. Set SHDN = 1
for shutdown mode.
48 48 48 ALLON
Enable-All-Channels Input. Drive ALLON high to enable all input
channels. When ALLON is low, only input channels selected as
active are powered. Select channels as active using the
configuration register.
9–12 7–12 I.C. Internally Connected. Connect I.C. to AGND. For factory use only.

MAX1322ECM+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 14-Bit 2Ch 526ksps 3V Precision ADC
Lifecycle:
New from this manufacturer.
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