MAX1322ECM+ Datasheet MAX1320ECM+, MAX1316ECM+, MAX1318ECM+ | P13-P15

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

______________________________________________________________________________________ 13

Detailed Description

The MAX1316–MAX1318/MAX1320–MAX1322/MAX1324-

MAX1326 are 14-bit ADCs. They offer two, four, or eight

(independently selectable) input channels, each with its

own T/H circuitry. Simultaneous sampling of all active

channels preserves relative phase information, making

these devices ideal for motor control and power monitor-

ing. These devices are available with 0 to +5V, ±5V, and

±10V input ranges. The 0 to +5V devices feature ±6V

fault-tolerant inputs. The ±5V and ±10V devices feature

±16.5V fault-tolerant inputs. Two channels convert in 2µs;

all eight channels convert in 3.8µs, with a maximum 8-

channel throughput of 263ksps per channel. Internal or

external reference and internal- or external-clock capabil-

ity offer great flexibility and ease of use. A write-only con-

figuration register can mask out unused channels, and a

shutdown feature reduces power. A 16.6MHz, 14-bit, par-

allel data bus outputs the conversion result. Figure 1

shows the functional diagram of these devices.

Analog Inputs

T/H

To preserve phase information across these multichan-

nel devices, each input channel has a dedicated

T/H amplifier.

Use a low-input source impedance to minimize gain-

error harmonic distortion. The time required for the T/H

to acquire an input signal depends on the input source

impedance. If the input signal’s source impedance is

high, the acquisition time lengthens and more time

must be allowed between conversions. The acquisition

time (t

) is the maximum time the device takes to

acquire the signal. Use the following formula to calcu-

late acquisition time:

= 10 (R

+ R

) x 6pF

where R

= 2.2kΩ, R

= the input signal’s source

impedance, and t

is never less than 180ns. A source

impedance of less than 100Ω does not significantly

affect the ADC’s performance.

Figure 1. Functional Diagram

MAX1316–MAX1318

MAX1320–MAX1322

MAX1324–MAX1326

CONVST

D13

MSV

DGND

SHDN

CLK

CH0

INTERFACE

AND

CONTROL

8 x 1

MUX

14-BIT

ADC

CH7

AGND

ALLON

REF

REF+

COM

REF-

S/H

8 x 14

SRAM

OUTPUT

DRIVERS

5kΩ

CONFIGURATION

2.500V

*SWITCH CLOSED ON UNIPOLAR DEVICES, OPEN ON BIPOLAR DEVICES

INTCLK/EXTCLK

EOC

EOLC

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

14 ______________________________________________________________________________________

To improve the input-signal bandwidth under AC condi-

tions, drive the input with a wideband buffer (>50MHz)

that can drive the ADC’s input capacitance and settle

quickly. For example, the MAX4265 can be used for +5V

unipolar devices, or the MAX4350 can be used for ±5V

bipolar inputs.

The T/H aperture delay is typically 13ns. The aperture-

delay mismatch between T/Hs of 50ps allows the relative

phase information of up to eight different inputs to be

preserved. Figure 2 shows a simplified equivalent input

circuit, illustrating the ADC’s sampling architecture.

Input Bandwidth

The input tracking circuitry has a 12MHz small-signal

bandwidth, making it is possible to digitize high-speed

transient events and measure periodic signals with

bandwidths exceeding the ADC’s sampling rate by using

undersampling techniques. To avoid high-frequency

signals being aliased into the frequency band of interest,

anti-alias filtering is recommended.

Input Range and Protection

These devices provide ±10V, ±5V, or 0 to +5V analog

input voltage ranges. Figure 2 shows the equivalent input

circuit. Overvoltage protection circuitry at the analog

input provides ±16.5V fault protection for the bipolar input

devices and ±6.0V fault protection for the unipolar input

devices. This fault-protection circuit limits the current

going into or out of the device to less than 50mA, provid-

ing an added layer of protection from momentary over-

voltage or undervoltage conditions at the analog input.

Power-Saving Modes

Shutdown Mode

During shutdown, the analog and digital circuits in the

device power down and the device draws less than

100µA from AV

, and less than 100µA from DV

Select shutdown mode using the SHDN input. Set SHDN

high to enter shutdown mode. After coming out of shut-

down, allow a 1ms wake-up time before making the first

conversion. When using an external clock, apply at least

20 clock cycles with CONVST high before making the first

conversion. When using internal-clock mode, wait at least

2µs before making the first conversion.

ALLON

ALLON is useful when some of the analog input channels

are selected (see the

Configuration Register

section).

Drive ALLON high to power up all input channel circuits,

regardless of whether they are selected as active by the

configuration register. Drive ALLON low or connect to

ground to power only the input channels selected as

active by the configuration register, saving 2mA per

channel (typ). The wake-up time for any channel turned

on with the configuration register is 2µs (typ) when

ALLON is low. The wake-up time with ALLON high is

only 0.01µs. New configuration-register information

does not become active until the next CONVST falling

edge. Therefore, when using software to control power

states (ALLON = 0), pulse CONVST low once before

applying the actual CONVST signal (Figure 3). With an

external clock, apply at least 15 clock cycles before

the second CONVST. If using internal-clock mode, wait

at least 1.5µs or until the first EOC before generating

the second CONVST.

Figure 2. Typical Input Circuit

CH_

BIAS

PAR

1pF

5pF

MAX1316–MAX1318

MAX1320–MAX1322

MAX1324–MAX1326

INPUT RANGE (V)

0 TO +5

±5

±10

R1 (kΩ)

3.33

6.67

13.33

R2 (kΩ)

5.00

2.86

2.35

BIAS

(V)

0.90

2.50

2.06

Table 1. Conversion Times Using the

Internal Clock

NUMBER OF CHANNELS

INTERNAL-CLOCK

CONVERSION TIME

1 1.6

2 1.9

3 2.2

4 2.5

5 2.8

6 3.1

7 3.4

8 3.7

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

______________________________________________________________________________________ 15

Clock Modes

These devices provide an internal clock of 10MHz

(typ). Alternatively, an external clock can be used.

Internal Clock

Internal-clock mode frees the microprocessor from the

burden of running the ADC conversion clock. For internal-

clock operation, connect INTCLK/EXTCLK to AV

and

connect CLK to DGND. Table 1 illustrates the total con-

version time using internal-clock mode.

External Clock

For external-clock operation, connect INTCLK/EXTCLK

to AGND and connect an external-clock source to CLK.

Note that INTCLK/EXTCLK is referenced to the analog

power supply, AV

. The external-clock frequency can

be up to 15MHz, with a duty cycle between 30% and

70%. Clock frequencies of 100kHz and lower can be

used, but the droop in the T/H circuits reduce linearity.

Selecting an Input Buffer

Most applications require an input buffer to achieve 14-

bit accuracy. Although slew-rate and bandwidth are

important, the most critical specification is settling time.

The sampling requires a relatively brief sampling inter-

val of 150ns. At the beginning of the acquisition, the

internal sampling capacitor array connects to CH_ (the

amplifier output), causing some output disturbance.

Ensure the amplifier is capable of settling to at least 14-

bit accuracy during this interval. Use a low-noise, low-

distortion, wideband amplifier (such as the MAX4350 or

MAX4265), which settles quickly and is stable with the

ADC’s capacitive load (in parallel with any bypass

capacitors on the analog inputs).

Applications Section

Digital Interface

The bidirectional, parallel, digital interface sets the 8-bit

configuration register (see the

Configuration Register

section) and outputs the 14-bit conversion result. The

interface includes the following control signals: chip

select (CS), read (RD), write (WR), end of conversion

(EOC), end of last conversion (EOLC), convert start

(CONVST), shutdown (SHDN), all on (ALLON), internal-

clock select (INTCLK /EXTCLK), and external-clock input

(CLK). Figures 4, 5, 6, 7, Table 4, and the

Timing

Characteristics

section show the operation of the inter-

face. D0–D7 are bidirectional, and D8–D13 are output

only. All bits are high impedance when RD = 1 or CS = 1.

Configuration Register

Enable channels as active by writing to the configuration

configuration register map directly to the channels, with

D0 controlling channel zero, and D7 controlling channel

seven. Setting any bit high activates the corresponding

input channel, while resetting any bit low deactivates the

corresponding channel. Devices with fewer than eight

channels contain some bits that have no function.

Figure 3. Software Channel Wake-Up Timing (ALLON = 0)

CONVST

D0–D7

CLK

EOC

EOLC

LATCH

ACQ

DUMMY

CONVERSION

START

ACTUAL

CONVERSION

START

DATA-IN

DATA-IN CHANGES ONE OR MORE CHANNELS

FROM POWER-DOWN TO ACTIVE MODE

12345 1415 1

>14 CYCLES

SAMPLE

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MAX1322ECM+

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 14-Bit 2Ch 526ksps 3V Precision ADC

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