MAX1322ECM+ Datasheet MAX1320ECM+, MAX1316ECM+, MAX1318ECM+ | P4-P6

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

4 _______________________________________________________________________________________

ELECTRICAL CHARACTERISTICS (continued)

= +5V, V

= +3V, V

AGND

= V

DGND

= 0, V

REF

= V

REFMS

= +2.5V (external reference), C

REF

= C

REFMS

= 0.1µF, C

REF+

REF-

= 0.1µF, C

REF+-to-REF-

= 2.2µF || 0.1µF, C

COM

= 2.2µF || 0.1µF, C

MSV

= 2.2µF || 0.1µF (unipolar devices, MAX1316/

MAX1317/MAX1318), MSV = AGND (bipolar devices, MAX1320/MAX1321/MAX1322/MAX1324/MAX1325/MAX1326), f

CLK

= 10MHz,

50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T

= T

MIN

to T

MAX

, unless otherwise noted. Typical val-

ues are at T

= +25°C.)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Input-Voltage Low V

0.3 x

Input Hysteresis 15 mV

Input Capacitance C

15 pF

Input Current I

= 0V or DV

±1µA

CLOCK-SELECT INPUT (INTCLK/EXTCLK)

Input-Voltage High

0.7 x

Input-Voltage Low

0.3 x

DIGITAL OUTPUTS (D0–D13, EOC, EOLC)

Output-Voltage High V

SOURCE

= 0.8mA

0.6

Output-Voltage Low V

SINK

= 1.6mA 0.4 V

Tri-State Leakage Current RD ≥ V

or CS ≥ V

0.06 1 µA

Tri-State Output Capacitance RD ≥ V

or CS ≥ V

15 pF

POWER SUPPLIES

Analog-Supply Voltage AV

4.75 5.25 V

Digital-Supply Voltage DV

2.70 5.25 V

Analog-Supply Current I

AVDD

All channels selected 46 56 mA

Digital-Supply Current I

DVDD

LOAD

= 100pF, all channels selected

(Note 6)

1 1.6 mA

AVDD

SHDN

= DV

, V

= float 10

Shutdown Current (Note 7)

DVDD

= V

= DV

, V

SHDN

= DV

0.1 2

µA

Power-Supply Rejection Ratio PSRR AV

= +4.75V to +5.75V (Note 8) 50 dB

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

_______________________________________________________________________________________ 5

Note 1: For the MAX1316/MAX1317/MAX1318, V

= 0 to +5V. For the MAX1320/MAX1321/MAX1322, V

= -5V to +5V. For the

MAX1324/MAX1325/MAX1326, V

= -10V to +10V.

Note 2: All channel performance is guaranteed by correlation to a single channel test.

Note 3: Offset nulled.

Note 4: The analog input resistance is terminated to an internal bias point. Calculate the analog input current using:

for V

within the input voltage range.

Note 5: Throughput rate is given per channel. Throughput rate is a function of clock frequency (f

CLK

= 10MHz). See the

Data

Throughput

section for more information.

Note 6: All analog inputs are driven with an FS 100kHz sine wave.

BIAS

−

TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Internal clock 1.6 1.8 µs

Time-to-First-Conversion Result t

CONV

External clock, Figure 6 16

Clock

cycles

Internal clock 0.3 0.36 µs

Time-to-Next-Conversion Result t

External clock, Figure 6 3

Clock

cycles

CONVST Pulse-Width Low

(Acquisition Time)

ACQ

(Note 9) 0.16 100 µs

CS Pulse Width t

30 ns

RD Pulse-Width Low t

30 ns

RD Pulse-Width High t

30 ns

WR Pulse-Width Low t

30 ns

CS to WR t

(Note 10) ns

WR to CS t

(Note 10) ns

CS to RD t

(Note 10) ns

RD to CS t

(Note 10) ns

Data-Access Time

(RD Low to Valid Data)

30 ns

Bus-Relinquish Time (RD High) t

30 ns

Internal clock 80 ns

EOC Pulse Width t

External clock, Figure 6 1

Clock

cycles

Input-Data Setup Time t

10 ns

Input-Data Hold Time t

10 ns

External-Clock Period t

0.08 10.00 µs

External-Clock High Period t

Logic sensitive to rising edges 20 ns

External-Clock Low Period t

Logic sensitive to rising edges 20 ns

External-Clock Frequency (Note 11) 0.1 12.5 MHz

Internal-Clock Frequency 10 MHz

CONVST High to CLK Edge t

20 (Note 12) ns

EOC Low to RD t

0ns

INTEGRAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1316 toc01

DIGITAL OUTPUT CODE

INL (LSB)

1228881924096

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

-1.00

0 16384

DIFFERENTIAL NONLINEARITY

vs. DIGITAL OUTPUT CODE

MAX1316 toc02

DIGITAL OUTPUT CODE

DNL (LSB)

1228881924096

-0.75

-0.50

-0.25

0.25

0.50

0.75

1.00

-1.00

0 16384

ANALOG SUPPLY CURRENT

vs. SUPPLY VOLTAGE

MAX1316 toc03

SUPPLY VOLTAGE (V)

SUPPLY CURRENT (mA)

5.125.004.87

4.75 5.25

SAMPLE

= 250ksps

ALL 8 CHANNELS

DRIVEN WITH FULL-

SCALE SINE WAVES

ANALOG SUPPLY CURRENT

vs. TEMPERATURE

MAX1316 toc04

TEMPERATURE (°C)

SUPPLY CURRENT (mA)

603510-15

-40 85

SAMPLE

250ksps

ALL 8 CHANNELS

DRIVEN WITH FULL-

SCALE SINE WAVES

SHUTDOWN CURRENT

vs. SUPPLY VOLTAGE

MAX1316 toc05

SUPPLY VOLTAGE (V)

SHUTDOWN CURRENT (µA)

4.53.5

0.2

0.4

0.6

0.8

2.5 5.5

ANALOG

SHUTDOWN

CURRENT

DIGITAL

SHUTDOWN

CURRENT

SHUTDOWN CURRENT

vs. TEMPERATURE

MAX1316 toc06

TEMPERATURE (°C)

SHUTDOWN CURRENT (µA)

603510-15

0.2

0.4

0.6

0.8

-40 85

ANALOG

SHUTDOWN

CURRENT

DIGITAL

SHUTDOWN

CURRENT

MAX1316–MAX1318/MAX1320–MAX1322/MAX1324–MAX1326

8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs

with ±10V, ±5V, and 0 to +5V Analog Input Ranges

6 _______________________________________________________________________________________

TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3) (continued)

Note 7: Shutdown current is measured with analog input floating. The large amplitude of the maximum shutdown current specifi-

cation is due to automatic test equipment limitations.

Note 8: Defined as the change in positive full scale caused by ±5% variation in the nominal supply voltage.

Note 9: CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor

droop.

Note 10: CS-to-WR and CS-to-RD pins are internally AND together. Setup and hold times do not apply.

Note 11: Minimum clock frequency is limited only by the internal T/H droop rate. Limit the time between the falling edge of CONVST

to the falling edge of EOLC to a maximum of 0.25ms.

Note 12: To avoid T/H droop degrading the sampled analog input signals, the first clock pulse should occur within 10µs of the ris-

ing edge of CONVST, and have a minimum clock frequency of 100kHz.

Typical Operating Characteristics

(AV

= +5V, DV

= +3V, AGND = DGND = 0V, V

REF

= V

REFMS

= +2.5V (external reference), see the

Typical Operating Circuits

sec-

tion, f

CLK

= 10MHz, 50% duty cycle, INTCLK/EXTCLK = AGND (external clock), SHDN = DGND, T

= +25°C, unless otherwise noted.)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

MAX1322ECM+

Mfr. #:

Buy MAX1322ECM+

Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 14-Bit 2Ch 526ksps 3V Precision ADC

Lifecycle:

New from this manufacturer.

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MAX1322ECM+

MAX1322ECM+

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