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P89LPC915HDH,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 13 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
P0.1/CIN2B/KBI1/AD10 1 I/O P0.1 — Port 0 bit 1.
I CIN2B — Comparator 2 positive input B.
I KBI1 — Keyboard input 1.
I AD10 — ADC1 channel 0 analog input.
P0.2/CIN2A/KBI2/AD11 16 I/O P0.2 — Port 0 bit 2.
I CIN2A — Comparator 2 positive input A.
I KBI2 — Keyboard input 2.
I AD11 — ADC1 channel 1 analog input.
P0.3/CIN1B/KBI3/AD12 15 I/O P0.3 — Port 0 bit 3.
I CIN1B — Comparator 1 positive input B.
I KBI3 — Keyboard input 3.
I AD12 — ADC1 channel 2 analog input.
P0.4/CIN1A/KBI4/AD13/DAC1 14 I/O P0.4 — Port 0 bit 4.
I CIN1A — Comparator 1 positive input A.
I KBI4 — Keyboard input 4.
I AD13 — ADC1 channel 3 analog input.
O DAC1 — DAC1 analog output.
P0.5/CMPREF/KBI5/CLKIN 13 I/O P0.5 — Port 0 bit 5.
I CMPREF — Comparator reference (negative) input.
I KBI5 — Keyboard input 5.
I CLKIN — External clock input.
P1.0 to P1.5 I/O, I
[1]
Port 1: Port 1 is an 6-bit I/O port with a user-configurable output type,
except for three pins as noted below. During reset Port 1 latches are
configured in the input only mode with the internal pull-up disabled. The
operation of the configurable Port 1 pins as inputs and outputs depends
upon the port configuration selected. Each of the configurable port pins
are programmed independently. Refer to
Section 8.13.1 “Port
configurations” and Table 15 “Static characteristics” for details. P1.2 to
P1.3 are open drain when used as outputs. P1.5 is input only.
All pins have Schmitt triggered inputs.
Port 1 also provides various special functions as described below:
P1.0/TXD 10 I/O P1.0 — Port 1 bit 0.
O TXD — Transmitter output for serial port.
P1.1/RXD 9 I/O P1.1 — Port 1 bit 1.
I RXD — Receiver input for serial port.
P1.2/T0/SCL 8 I/O P1.2 — Port 1 bit 2 (open-drain when used as output).
I/O T0 — Timer/counter 0 external count input or overflow output
(open-drain when used as output).
I/O SCL — I
2
C serial clock input/output.
P1.3/
INT0/SDA 7 I/O P1.3 — Port 1 bit 3 (open-drain when used as output).
I
INT0 — External interrupt 0 input.
I/O SDA — I
2
C serial data input/output.
P1.5/
RST 3 I P1.5 — Port 1 bit 5 (input only).
Table 5. P89LPC916 pin description
…continued
Symbol Pin Type Description
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 14 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
[1] Input/output for P1.0 to P1.3. Input for P1.5.
I RST — External Reset input during power-on or if selected via UCFG1.
When functioning as a reset input, a LOW on this pin resets the
microcontroller, causing I/O ports and peripherals to take on their
default states, and the processor begins execution at address 0. Also
used during a power-on sequence to force ISP mode. When using an
oscillator frequency above 12 MHz, the reset input function of P1.5
must be enabled. An external circuit is required to hold the device
in reset at power-up until V
DD
has reached its specified level. When
system power is removed V
DD
will fall below the minimum
specified operating voltage. When using an oscillator frequency
above 12 MHz, in some applications, an external brownout detect
circuit may be required to hold the device in reset when V
DD
falls
below the minimum specified operating voltage.
P2.2 to P2.5 Port 2: Port 2 is a 4-bit I/O port with a user-configurable output type.
During reset Port 2 latches are configured in the input only mode with
the internal pull-up disabled. The operation of Port 2 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to
Section 8.13.1 “Port configurations”
and
Table 15 “Static characteristics” for details.
All pins have Schmitt triggered inputs.
Port 2 also provides various special functions as described below:
P2.2/MOSI 6 I/O P2.2 — Port 2 bit 2.
I/O MOSI — SPI master out slave in. When configured as master, this pin is
output; when configured as slave, this pin is input.
P2.3/MISO 5 I/O P2.3 — Port 2 bit 3.
I/O MISO — When configured as master, this pin is input, when configured
as slave, this pin is output.
P2.4/
SS 2 I/O P2.4 — Port 2 bit 4.
I/O
SS — SPI Slave select.
P2.5/SPICLK 11 I/O P2.5 — Port 2 bit 5.
I/O SPICLK — SPI clock. When configured as master, this pin is output;
when configured as slave, this pin is input.
V
SS
4IGround: 0 V reference.
V
DD
12 I Power supply: This is the power supply voltage for normal operation as
well as Idle and Power-down modes.
Table 5. P89LPC916 pin description
…continued
Symbol Pin Type Description
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 15 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 6. P89LPC917 pin description
Symbol Pin Type Description
P0.0 to P0.5, P0.7 I/O Port 0: Port 0 is a 7-bit I/O port with a user-configurable output type.
During reset Port 0 latches are configured in the input only mode with the
internal pull-up disabled. The operation of Port 0 pins as inputs and
outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to
Section 8.13.1 “Port configurations”
and
Table 15 “Static characteristics” for details.
The Keypad Interrupt feature operates with Port 0 pins.
All pins have Schmitt triggered inputs.
Port 0 also provides various special functions as described below:
P0.0/CMP2/KBI0 2 I/O P0.0 — Port 0 bit 0.
O CMP2 — Comparator 2 output.
I KBI0 — Keyboard input 0.
P0.1/CIN2B/KBI1/AD10 1 I/O P0.1 — Port 0 bit 1.
I CIN2B — Comparator 2 positive input B.
I KBI1 — Keyboard input 1.
I AD10 — ADC1 channel 0 analog input.
P0.2/CIN2A/KBI2/AD11 16 I/O P0.2 — Port 0 bit 2.
I CIN2A — Comparator 2 positive input A.
I KBI2 — Keyboard input 2.
I AD11 — ADC1 channel 1 analog input.
P0.3/CIN1B/KBI3/AD12 15 I/O P0.3 — Port 0 bit 3.
I CIN1B — Comparator 1 positive input B.
I KBI3 — Keyboard input 3.
I AD12 — ADC1 channel 2 analog input.
P0.4/CIN1A/KBI4/AD13/
DAC1
14 I/O P0.4 — Port 0 bit 4.
I CIN1A — Comparator 1 positive input A.
I KBI4 — Keyboard input 4.
I AD13 — ADC1 channel 3 analog input.
O DAC1 — DAC1 analog output.
P0.5/CMPREF/KBI5 13 I/O P0.5 — Port 0 bit 5.
I CMPREF — Comparator reference (negative) input.
I KBI5 — Keyboard input 5.
I CLKIN — External clock input.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75

P89LPC915HDH,129

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Buy P89LPC915HDH,129
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 8B MCU 80C51 2KB 3V FL 8B A/D CONVRT
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New from this manufacturer.
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