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P89LPC915HDH,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 61 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
[1] Parameters are valid over ambient temperature range unless otherwise specified.
[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
t
SPILEAD
SPI enable lead time see Figure 25, 26
slave 250 - 250 - ns
t
SPILAG
SPI enable lag time see Figure 25, 26
slave 250 - 250 - ns
t
SPICLKH
SPICLK HIGH time see Figure 23, 24,
25, 26
master
2
⁄
CCLK
- 165 - ns
slave
3
⁄
CCLK
- 250 - ns
t
SPICLKL
SPICLK LOW time see Figure 23, 24,
25, 26
master
2
⁄
CCLK
- 165 - ns
slave
3
⁄
CCLK
- 250 - ns
t
SPIDSU
SPI data set-up time see Figure 23, 24,
25, 26
master or slave 100 - 100 - ns
t
SPIDH
SPI data hold time see Figure 23, 24,
25, 26
master or slave 100 - 100 - ns
t
SPIA
SPI access time see Figure 25, 26
slave 0 120 0 120 ns
t
SPIDIS
SPI disable time see Figure 25, 26
slave 0 240 - 240 ns
t
SPIDV
SPI enable to output data valid
time
see Figure 23, 24,
25, 26
slave - 240 - 240 ns
master - 167 - 167 ns
t
SPIOH
SPI output data hold time see Figure 23, 24,
25, 26
0-0-ns
t
SPIR
SPI rise time see Figure 23, 24,
25, 26
SPI outputs
(SPICLK, MOSI, MISO)
- 100 - 100 ns
SPI inputs
(SPICLK, MOSI, MISO,
SS)
- 2000 - 2000 ns
t
SPIF
SPI fall time see Figure 23, 24,
25, 26
SPI outputs
(SPICLK, MOSI, MISO)
- 100 - 100 ns
SPI inputs
(SPICLK, MOSI, MISO,
SS)
- 2000 - 2000 ns
Table 16. Dynamic characteristics (12 MHz)
…continued
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C, or
−
40
°
C to +125
°
C (see Table 3 on page 3), unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
=12MHz Unit
Min Max Min Max
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 62 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Table 17. Dynamic characteristics (18 MHz)
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C, or
−
40
°
C to +125
°
C (see Table 3 on page 3), unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
= 18 MHz Unit
Min Max Min Max
f
osc(RC)
internal RC oscillator frequency industrial 7.189 7.557 7.189 7.557 MHz
extended 7.004 7.741 7.004 7.741 MHz
f
osc(WD)
internal watchdog oscillator
frequency
320 520 320 520 kHz
f
CLKLP
low power select clock
frequency
0 8 - - MHz
Glitch filter
t
gr
glitch rejection time P1.5/RST pin - 50 - 50 ns
any pin except
P1.5/
RST
- 15 - 15 ns
t
sa
signal acceptance time P1.5/RST pin 125 - 125 - ns
any pin except
P1.5/
RST
50 - 50 - ns
External clock
f
osc
oscillator frequency 0 18 - - MHz
T
cy(clk)
clock cycle time see Figure 28 55 - - - ns
t
CHCX
clock HIGH time see Figure 28 22 T
cy(CLK)
− t
CLCX
22 - ns
t
CLCX
clock LOW time see Figure 28 22 T
cy(CLK)
− t
CHCX
22 - ns
t
CLCH
clock rise time see Figure 28 -5-5ns
t
CHCL
clock fall time see Figure 28 -5-5ns
Shift register (UART mode 0)
T
XLXL
serial port clock cycle time see Figure 27 16T
cy(CLK)
- 888 - ns
t
QVXH
output data set-up to clock
rising edge time
see Figure 27 13T
cy(CLK)
- 722 - ns
t
XHQX
output data hold after clock
rising edge time
see Figure 27 -T
cy(CLK)
+ 20 - 75 ns
t
XHDX
input data hold after clock rising
edge time
see Figure 27 -0-0ns
t
XHDV
input data valid to clock rising
edge time
see Figure 27 150 - 150 - ns
SPI interface
f
SPI
SPI operating frequency
slave 0
CCLK
⁄
6
0 3.0 MHz
master -
CCLK
⁄
4
- 4.5 MHz
T
SPICYC
SPI cycle time see Figure 23, 24,
25, 26
slave
6
⁄
CCLK
- 333 - ns
master
4
⁄
CCLK
- 222 - ns
t
SPILEAD
SPI enable lead time see Figure 25, 26
slave 250 - 250 - ns
t
SPILAG
SPI enable lag time see Figure 25, 26 250 - 250 - ns
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 63 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
[1] Parameters are valid over ambient temperature range unless otherwise specified.
[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
t
SPICLKH
SPICLK HIGH time see Figure 23, 24,
25, 26
master
2
⁄
CCLK
- 111 - ns
slave
3
⁄
CCLK
- 167 - ns
t
SPICLKL
SPICLK LOW time see Figure 23, 24,
25, 26
master
2
⁄
CCLK
- 111 - ns
slave
3
⁄
CCLK
- 167 - ns
t
SPIDSU
SPI data set-up time see Figure 23, 24,
25, 26
master or slave 100 - 100 - ns
t
SPIDH
SPI data hold time see Figure 23, 24,
25, 26
master or slave 100 - 100 - ns
t
SPIA
SPI access time see Figure 25, 26
slave 0 80 0 80 ns
t
SPIDIS
SPI disable time see Figure 25, 26
slave 0 160 - 160 ns
t
SPIDV
SPI enable to output data valid
time
see Figure 23, 24,
25, 26
slave - 160 - 160 ns
master - 111 - 111 ns
t
SPIOH
SPI output data hold time see Figure 23, 24,
25, 26
0-0-ns
t
SPIR
SPI rise time see Figure 23, 24,
25, 26
SPI outputs
(SPICLK, MOSI, MISO)
- 100 - 100 ns
SPI inputs
(SPICLK, MOSI, MISO,
SS)
- 2000 - 2000 ns
t
SPIF
SPI fall time see Figure 23, 24,
25, 26
SPI outputs
(SPICLK, MOSI, MISO)
- 100 - 100 ns
SPI inputs
(SPICLK, MOSI, MISO,
SS)
- 2000 - 2000 ns
Table 17. Dynamic characteristics (18 MHz)
…continued
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C, or
−
40
°
C to +125
°
C (see Table 3 on page 3), unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
= 18 MHz Unit
Min Max Min Max
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75

P89LPC915HDH,129

Mfr. #:
Buy P89LPC915HDH,129
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 8B MCU 80C51 2KB 3V FL 8B A/D CONVRT
Lifecycle:
New from this manufacturer.
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