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P89LPC915HDH,129

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 58 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
11. Static characteristics
Table 15. Static characteristics
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C, or
−
40
°
C to +125
°
C (see Table 3 on page 3), unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
I
DD(oper)
operating supply current V
DD
= 3.6 V; f
osc
= 12 MHz
[2]
- 7 13 mA
V
DD
= 3.6 V; f
osc
= 18 MHz
[2]
-1116mA
I
DD(idle)
Idle mode supply current V
DD
= 3.6 V; f
osc
= 12 MHz
[2]
- 3.6 4.8 mA
V
DD
= 3.6 V; f
osc
= 18 MHz
[2]
-46mA
I
DD(pd)
power supply current,
power-down mode, voltage
comparators powered-down
V
DD
= 3.6 V, industrial
[2]
-4570µA
V
DD
= 3.6 V, extended
[2]
- 150 µA
I
DD(tpd)
total Power-down mode
supply current
V
DD
= 3.6 V, industrial
[3]
- <0.1 5 µA
V
DD
= 3.6 V, extended
[3]
--50µA
(dV/dt)
r
rise rate of V
DD
- - 2 mV/µs
(dV/dt)
f
fall rate of V
DD
- - 50 mV/µs
V
POR
power-on reset voltage - - 0.2 V
V
DDR
data retention voltage 1.5 - - V
V
th(HL)
HIGH-LOW threshold
voltage
except SCL, SDA 0.22V
DD
0.4V
DD
-V
V
IL
LOW-level input voltage SCL, SDA only −0.5 - 0.3V
DD
V
V
th(LH)
LOW-HIGH threshold
voltage
except SCL, SDA - 0.6V
DD
0.7V
DD
V
V
IH
HIGH-level input voltage SCL, SDA only 0.7V
DD
- 5.5 V
V
hys
hysteresis voltage port 1 - 0.2V
DD
-V
V
OL
LOW-level output voltage I
OL
= 20 mA; all ports
except SCL, SDA
[4]
- 0.6 1.0 V
I
OL
= 10 mA; all ports
except SCL, SDA
- 0.2 0.3 V
I
OL
= 3.2 mA; all ports
except SCL, SDA
- 0.2 0.3 V
V
OH
HIGH-level output voltage I
OH
= −8 mA;
push-pull mode; all ports
except SCL, SDA
V
DD
− 1- - V
I
OH
= −3.2 mA;
push-pull mode; all ports
except SCL, SDA
V
DD
− 0.7 V
DD
− 0.4 - V
I
OH
= −20 µA;
quasi-bidirectional mode;
all ports except SCL, SDA
V
DD
− 0.3 V
DD
− 0.2 - V
V
xtal
crystal voltage voltage on XTAL1, XTAL2
pins with respect to V
SS
−0.5 - +4.0 V
V
n
voltage on any pin (except
XTAL1, XTAL2, V
DD
)
with respect to V
SS
[5]
−0.5 - +5.5 V
C
iss
input capacitance
[6]
- - 15 pF
I
IL
logical 0 input current V
I
= 0.4 V
[7]
--−80 µA
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 59 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
[1] Typical ratings are not guaranteed. The values listed are at room temperature, 3 V.
[2] The I
DD(oper)
,I
DD(idle)
, and I
DD(pd)
specifications are measured using an external clock with the following functions disabled: comparators,
real-time clock, and watchdog timer.
[3] The I
DD(tpd)
specification is measured using an external clock with the following functions disabled: comparators, real-time clock,
brownout detect, and watchdog timer.
[4] See Section 10 “Limiting values” for steady state (non-transient) limits on I
OL
or I
OH
. If I
OL
/I
OH
exceeds the test condition, V
OL
/V
OH
may
exceed the related specification.
[5] This specification can be applied to pins which have A/D input or analog comparator input functions when the pin is not being used for
those analog functions. When the pin is being used as an analog input pin, the maximum voltage on the pin must be limited to 4.0 V with
respect to V
SS
.
[6] Pin capacitance is characterized but not tested.
[7] Measured with port in quasi-bidirectional mode.
[8] Measured with port in high-impedance mode.
[9] Port pins source a transition current when used in quasi-bidirectional mode and externally driven from logic 1 to logic 0. This current is
highest when V
I
is approximately 2 V.
I
LI
input leakage current V
I
=V
IL
,V
IH
or V
th(HL)
[8]
--±10 µA
I
TL
logical 1-to-0 transition
current, all ports
V
I
= 1.5 V at V
DD
= 3.6 V
[9]
−30 - −450 µA
R
RST(int)
internal pull-up resistance
on pin
RST
10 - 30 kΩ
V
bo
brownout trip voltage 2.4 V < V
DD
< 3.6 V; with
BOV = 1, BOPD = 0
2.40 - 2.70 V
V
ref(bg)
band gap reference voltage 1.11 1.23 1.34 V
TC
bg
band gap temperature
coefficient
- 10 20 ppm/°C
Table 15. Static characteristics
…continued
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C, or
−
40
°
C to +125
°
C (see Table 3 on page 3), unless otherwise specified.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 60 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
12. Dynamic characteristics
Table 16. Dynamic characteristics (12 MHz)
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
−
40
°
C to +85
°
C, or
−
40
°
C to +125
°
C (see Table 3 on page 3), unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
=12MHz Unit
Min Max Min Max
f
osc(RC)
internal RC oscillator frequency industrial 7.189 7.557 7.189 7.557 MHz
extended 7.004 7.741 7.004 7.741 MHz
f
osc(WD)
internal watchdog oscillator
frequency
320 520 320 520 kHz
f
CLKLP
low power select clock
frequency
0 8 - - MHz
Glitch filter
t
gr
glitch rejection time P1.5/RST pin - 50 - 50 ns
any pin except
P1.5/
RST
- 15 - 15 ns
t
sa
signal acceptance time P1.5/RST pin 125 - 125 - ns
any pin except
P1.5/
RST
50 - 50 - ns
External clock
f
osc
oscillator frequency 0 12 - - MHz
T
cy(clk)
clock cycle time see Figure 28 83 - - - ns
t
CHCX
clock HIGH time see Figure 28 33 T
cy(CLK)
− t
CLCX
33 - ns
t
CLCX
clock LOW time see Figure 28 33 T
cy(CLK)
− t
CHCX
33 - ns
t
CLCH
clock rise time see Figure 28 -8-8ns
t
CHCL
clock fall time see Figure 28 -8-8ns
Shift register (UART mode 0)
T
XLXL
serial port clock cycle time see Figure 27 16T
cy(CLK)
- 1333 - ns
t
QVXH
output data set-up to clock rising
edge time
see Figure 27 13T
cy(CLK)
- 1083 - ns
t
XHQX
output data hold after clock
rising edge time
see Figure 27 -T
cy(CLK)
+ 20 - 103 ns
t
XHDX
input data hold after clock rising
edge time
see Figure 27 -0-0ns
t
XHDV
input data valid to clock rising
edge time
see Figure 27 150 - 150 - ns
SPI interface
f
SPI
SPI operating frequency
slave 0
CCLK
⁄
6
0 2.0 MHz
master -
CCLK
⁄
4
- 3.0 MHz
T
SPICYC
SPI cycle time see Figure 23, 24,
25, 26
slave
6
⁄
CCLK
- 500 - ns
master
4
⁄
CCLK
- 333 - ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75

P89LPC915HDH,129

Mfr. #:
Buy P89LPC915HDH,129
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 8B MCU 80C51 2KB 3V FL 8B A/D CONVRT
Lifecycle:
New from this manufacturer.
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