P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 34 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
disable bit, EA, which disables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are pending at the start of an instruction, the request of higher priority level is
serviced.
If requests of the same priority level are pending at the start of an instruction, an internal
polling sequence determines which request is serviced. This is called the arbitration
ranking. Note that the arbitration ranking is only used to resolve pending requests of the
same priority level.
8.12.1 External interrupt inputs
The P89LPC915 and P89LPC917 have two external interrupt inputs. The P89LPC916 has
one external interrupt input. These external interrupt inputs are identical to those present
on the standard 80C51 microcontrollers. All three devices also have the Keypad Interrupt
function.
These external interrupts can be programmed to be level-triggered or edge-triggered by
setting or clearing bit IT1 or IT0 in Register TCON.
In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle
and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an
interrupt request.
If an external interrupt is enabled when the P89LPC915/916/917 is put into Power-down
or Idle mode, the interrupt will cause the processor to wake-up and resume operation.
Refer to Section 8.15 “Power reduction modes” for details.
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 35 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
Fig 12. Interrupt sources, interrupt enables, and power-down wake-up sources
002aab408
IE0
EX0
IE1
EX1
BOF
EBO
KBIF
EKBI
interrupt
to CPU
wake-up
(if in power-down)
EWDRT
CMF2
CMF1
EC
EA (IE0.7)
TF1
ET1
TI_0 and RI_0/RI_0
ES/ESR
TI_0
EST
SI
EI2C
SPIF
ESPI
RTCF
ERTC
(RTCCON.1)
WDOVF
TF0
ET0
TI_1 and RI_1/RI_1
ES1/ESR1
TI_1
EADC
EST1
ENADCI0
ADCI0
ENBI0
BNDI0
P89LPC915_916_917_5 © NXP B.V. 2009. All rights reserved.
Product data sheet Rev. 05 — 15 December 2009 36 of 75
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
8.13 I/O ports
The P89LPC916 and P89LPC917 devices have three I/O ports: Port 0, Port 1, and Port 2.
The exact number of I/O pins available depends upon the clock and reset options chosen,
as shown in Table 11.
[1] Required for operation above 12 MHz.
The P89LPC915 has two I/O ports: Port 0 and Port 1. The exact number of I/O pins
available depends upon the clock and reset options chosen, as shown in Table 12.
[1] Required for operation above 12 MHz.
8.13.1 Port configurations
All but three I/O port pins on the P89LPC915/916/917 may be configured by software to
one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port
outputs), push-pull, open drain, and input-only. Two configuration registers for each port
select the output type for each port pin.
1. P1.5 (RST) can only be an input and cannot be configured.
2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.
8.13.1.1 Quasi-bidirectional output configuration
Quasi-bidirectional output type can be used as both an input and output without the need
to reconfigure the port. This is possible because when the port outputs a logic HIGH, it is
weakly driven, allowing an external device to pull the pin LOW. When the pin is driven
LOW, it is driven strongly and able to sink a fairly large current. These features are
somewhat similar to an open-drain output except that there are three pull-up transistors in
the quasi-bidirectional output that serve different purposes.
Table 11. Number of I/O pins available (P89LPC916 and P89LPC917)
Clock source Reset option Number of I/O
pins (16-pin
package)
RC oscillator or watchdog
oscillator
No external reset (except during
power-up)
14
External RST pin supported 13
External clock input No external reset (except during
power-up)
13
External
RST pin supported
[1]
12
Table 12. Number of I/O pins available (P89LPC915)
Clock source Reset option Number of I/O
pins (14-pin
package)
RC oscillator or watchdog
oscillator
No external reset (except during
power-up)
12
External RST pin supported 11
External clock input No external reset (except during
power-up)
11
External
RST pin supported
[1]
10

P89LPC915HDH,129

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU 8B MCU 80C51 2KB 3V FL 8B A/D CONVRT
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