IDT 89HPES24NT24G2 Datasheet
14 of 35 December 17, 2013
PCI Express Interface
(cont.)
PE21TN[0] O PCIe
differential
Serial Link
PE21TP[0] O
PE22RN[0] I
PE22RP[0] I
PE22TN[0] O
PE22TP[0] O
PE23RN[0] I
PE23RP[0] I
PE23TN[0] O
PE23TP[0] O
Reference Clocks GCLKN[1:0] I HCSL Diff. Clock
Input
Refer to Table 11
Note: Unused port
clock pins should be
connected to Vss on
the board.
GCLKP[1:0] I
P08CLKN I
P08CLKP I
P16CLKN I
P16CLKP I
SMBus MSMBCLK I/O LVTTL STI
3
Note: When unused, these signals must
be pulled up on the board using an
external resistor or current source in
accordance with the SMBus specifica-
tion.
MSMBDAT I/O STI
SSMBADDR[2,1] I pull-up
SSMBCLK I/O STI Note: When unused, these signals must
be pulled up on the board using an
external resistor or current source in
accordance with the SMBus specifica-
tion.
SSMBDAT I/O STI
General Purpose I/O GPIO[8:0] I/O LVTTL STI, High
Drive
pull-up Unused pins can be left
floating.
Stack Configuration STK2CFG[4:0] I LVTTL Input pull-down Unused pins can be left
floating.
STK3CFG[4:0] I pull-down
System Pins CLKMODE[1:0] I LVTTL Input pull-up Unused pins can be left
floating.
GCLKFSEL I pull-down
PERSTN I Schmitt trigger
RSTHALT I pull-down Unused pins can be left
floating.
SWMODE[3:0] I pull-down
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
Table 10 Pin Characteristics (Part 4 of 5)
