89H24NT24G2ZCHLGI Datasheet 89H24NT24G2ZCHLGI, 89H24NT24G2ZBHLGI, 89H24NT24G2ZCHLG | P7-P9

IDT 89HPES24NT24G2 Datasheet

7 of 35 December 17, 2013

PE21TN[0]

PE21TP[0]

O PCI Express Port 21 Serial Data Transmit. Differential PCI Express transmit pair for

port 21.

PE22RN[0]

PE22RP[0]

I PCI Express Port 22 Serial Data Receive. Differential PCI Express receive pair for

port 22.

PE22TN[0]

PE22TP[0]

O PCI Express Port 22 Serial Data Transmit. Differential PCI Express transmit pair for

port 22.

PE23RN[0]

PE23RP[0]

I PCI Express Port 23 Serial Data Receive. Differential PCI Express receive pair for

port 23.

PE23TN[0]

PE23TP[0]

O PCI Express Port 23 Serial Data Transmit. Differential PCI Express transmit pair for

port 23.

Signal Type Name/Description

GCLKN[1:0]

GCLKP[1:0]

I Global Reference Clock. Differential reference clock input pairs. This

clock is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic. The frequency of the differential reference

clock is determined by the GCLKFSEL signal.

Note: Both pairs of the Global Reference Clocks must be connected to and

derived from the same clock source. Refer to the Overview section of

Chapter 2 in the PES24NT24G2 User Manual for additional details.

P08CLKN

P08CLKP

I Port Reference Clock. Differential reference clock pair associated with

port 8.

P16CLKN

P16CLKP

I Port Reference Clock. Differential reference clock pair associated with

port 16.

Table 3 Reference Clock Pins

Signal Type Name/Description

MSMBCLK I/O Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the

master SMBus. It is active and generating the clock only when the EEPROM or I/O

Expanders are being accessed.

MSMBDAT I/O Master SMBus Data. This bidirectional signal is used for data on the master SMBus.

SSMBADDR[2,1] I Slave SMBus Address. These pins determine the SMBus address to which the slave

SMBus interface responds.

SSMBCLK I/O Slave SMBus Clock. This bidirectional signal is used to synchronize transfers on the

slave SMBus.

SSMBDAT I/O Slave SMBus Data. This bidirectional signal is used for data on the slave SMBus.

Table 4 SMBus Interface Pins

Signal Type Name/Description

Table 2 PCI Express Interface Pins (Part 3 of 3)

IDT 89HPES24NT24G2 Datasheet

8 of 35 December 17, 2013

Signal Type Name/Description

GPIO[0] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: PART0PERSTN

1st Alternate function pin type: Input/Output

1st Alternate function: Assertion of this signal initiated a partition funda-

mental reset in the corresponding partition.

2nd Alternate function pin name: P16LINKUPN

2nd Alternate function pin type: Output

2nd Alternate function: Port 16 Link Up Status output.

GPIO[1] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: PART1PERSTN

1st Alternate function pin type: Input/Output

1st Alternate function: Assertion of this signal initiated a partition funda-

mental reset in the corresponding partition.

2nd Alternate function pin name: P16ACTIVEN

2nd Alternate function pin type: Output

2nd Alternate function: Port 16 Link Active Status Output.

GPIO[2] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: PART2PERSTN

1st Alternate function pin type: Input/Output

1st Alternate function: Assertion of this signal initiated a partition funda-

mental reset in the corresponding partition.

2nd Alternate function pin name: P4LINKUPN

2nd Alternate function pin type: Output

2nd Alternate function: Port 4 Link Up Status output.

GPIO[3] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: PART3PERSTN

1st Alternate function pin type: Input/Output

1st Alternate function: Assertion of this signal initiated a partition funda-

mental reset in the corresponding partition.

2nd Alternate function pin name: P4ACTIVEN

2nd Alternate function pin type: Output

2nd Alternate function: Port 4 Link Active Status Output.

GPIO[4] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: FAILOVER0

1st Alternate function pin type: Input

1st Alternate function: When this signal changes state and the correspond-

ing failover capability is enabled, a failover event is signaled.

2nd Alternate function pin name: P0LINKUPN

2nd Alternate function pin type: Output

2nd Alternate function: Port 0 Link Up Status output.

GPIO[5] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: GPEN

1st Alternate function pin type: Output

1st Alternate function: Hot-plug general purpose even output.

2nd Alternate function pin name: P0ACTIVEN

2nd Alternate function pin type: Output

2nd Alternate function: Port 0 Link Active Status Output.

Table 5 General Purpose I/O Pins (Part 1 of 2)

IDT 89HPES24NT24G2 Datasheet

9 of 35 December 17, 2013

GPIO[6] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: FAILOVER1

1st Alternate function pin type: Input

1st Alternate function: When this signal changes state and the correspond-

ing failover capability is enabled, a failover event is signaled.

2nd Alternate function pin name: FAILOVER3

2nd Alternate function pin type: Input

2nd Alternate function: When this signal changes state and the correspond-

ing failover capability is enabled, a failover event is signaled.

GPIO[7] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: FAILOVER2

1st Alternate function pin type: Input

1st Alternate function: When this signal changes state and the correspond-

ing failover capability is enabled, a failover event is signaled.

2nd Alternate function pin name: P8LINKUPN

2nd Alternate function pin type: Output

2nd Alternate function: Port 8 Link Up Status output.

GPIO[8] I/O General Purpose I/O.

This pin can be configured as a general purpose I/O pin.

1st Alternate function pin name: IOEXPINTN

1st Alternate function pin type: Input

1st Alternate function: IO expander interrupt.

2nd Alternate function pin name: P8ACTIVEN

2nd Alternate function pin type: Output

2nd Alternate function: Port 8 Link Active Status Output.

Signal Type Name/Description

STK2CFG[4:0] I Stack 2 Configuration. These pins select the configuration of stack 2.

STK3CFG[4:0] I Stack 3 Configuration. These pins select the configuration of stack 3.

Table 6 Stack Configuration Pins

Signal Type Name/Description

CLKMODE[1:0] I Clock Mode. These signals determine the port clocking mode used by ports of the

device.

GCLKFSEL I Global Clock Frequency Select. These signals select the frequency of the GCLKP

and GCLKN signals.

0x0 100 MHz

0x1 125 MHz

Table 7 System Pins (Part 1 of 2)

Signal Type Name/Description

Table 5 General Purpose I/O Pins (Part 2 of 2)

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P35

89H24NT24G2ZCHLGI

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PCI Interface IC PCIE SWITCH

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