IDT 89HPES24NT24G2 Datasheet
16 of 35 December 17, 2013
Logic Diagram — PES24NT24G2
Figure 3 PES24NT24G2 Logic Diagram
JTAG_TCK
GPIO[8:0]
9
General Purpose
I/O
MSMBCLK
MSMBDAT
Master
SMBus Interface
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST_N
JTAG Pins
P08CLKN
P08CLKP
PE00RP[0]
PE00RN[0]
PE00TP[0]
PE00TN[0]
PE07RP[0]
PE07RN[0]
PCIe Switch
SerDes Input
Port 7
PE23RP[0]
PE23RN[0]
PCIe Switch
SerDes Input
PE23TP[0]
PE23TN[0]
PCIe Switch
SerDes Output
Port 23
Port 23
PES24NT24G2
2
PCIe Switch
SerDes Input
Port 0
PCIe Switch
SerDes Output
Port 0
...
Global
Reference Clocks
GCLKN[1:0]
GCLKP[1:0]
GCLKFSEL
V
DD
CORE
V
DD
I/O
V
DD
PEA
Power/Ground
V
SS
V
DD
PEHA
V
DD
PETA
RSTHALT
System
Pins
SWMODE[3:0]
4
CLKMODE[1:0]
PERSTN
2
...
SSMBCLK
SSMBDAT
Slave
SMBus Interface
SSMBADDR[2,1]
STK2CFG[4:0]
5
STK3CFG[4:0]
5
Stack
Configuration
REFRES[7:0]
SerDes
Reference
Resistors
REFRESPLL
8
...
PE09RP[0]
PE09RN[0]
PCIe Switch
SerDes Input
Port 9
PE08RP[0]
PE08RN[0]
PCIe Switch
SerDes Input
Port 8
Note that in addition to Port 8, Port 16
also has port clocks, P16CLKN/P.
IDT 89HPES24NT24G2 Datasheet
17 of 35 December 17, 2013
System Clock Parameters
Values based on systems running at recommended supply voltages and operating temperatures, as shown in Tables 16 and 15.
Note: Refclk jitter compliant to PCIe Gen2 Common Clock architecture is adequate for the GCLKN/P[x] and PE[x]CLKN/P pins of this IDT
PCIe switch. This same jitter specification is applicable when interfacing the switch to another IDT switch in a Separate (Non-Common)
Clock architecture.
AC Timing Characteristics
Parameter Description Condition Min Typical Max Unit
Refclk
FREQ
Input reference clock frequency range 100 125
1
1.
The input clock frequency will be either 100 or 125 MHz depending on signal GCLKFSEL.
MHz
T
C-RISE
Rising edge rate Differential 0.6 4 V/ns
T
C-FALL
Falling edge rate Differential 0.6 4 V/ns
V
IH
Differential input high voltage Differential +150 mV
V
IL
Differential input low voltage Differential -150 mV
V
CROSS
Absolute single-ended crossing point
voltage
Single-ended +250 +550 mV
V
CROSS-DELTA
Variation of V
CROSS
over all rising clock
edges
Single-ended +140 mV
V
RB
Ring back voltage margin Differential -100 +100 mV
T
STABLE
Time before V
RB
is allowed Differential 500 ps
T
PERIOD-AVG
Average clock period accuracy -300 2800 ppm
T
PERIOD-ABS
Absolute period, including spread-spec-
trum and jitter
9.847 10.203 ns
T
CC-JITTER
Cycle to cycle jitter 150 ps
V
MAX
Absolute maximum input voltage +1.15 V
V
MIN
Absolute minimum input voltage -0.3 V
Duty Cycle Duty cycle 40 60 %
Rise/Fall Matching Single ended rising Refclk edge rate ver-
sus falling Refclk edge rate
20 %
Z
C-DC
Clock source output DC impedance 40 60
Table 11 Input Clock Requirements
Parameter Description
Gen 1 Gen 2
Units
Min
1
Typ
1
Max
1
Min
1
Typ
1
Max
1
PCIe Transmit
UI Unit Interval 399.88 400 400.12 199.94 200 200.06 ps
T
TX-EYE
Minimum Tx Eye Width 0.75 0.75 UI
T
TX-EYE-MEDIAN-to-
MAX-JITTER
Maximum time between the jitter median and maxi-
mum deviation from the median
0.125 UI
Table 12 PCIe AC Timing Characteristics (Part 1 of 2)
IDT 89HPES24NT24G2 Datasheet
18 of 35 December 17, 2013
T
TX-RISE
, T
TX-FALL
TX Rise/Fall Time: 20% - 80% 0.125 0.15 UI
T
TX- IDLE-MIN
Minimum time in idle 20 20 UI
T
TX-IDLE-SET-TO-
IDLE
Maximum time to transition to a valid Idle after sending
an Idle ordered set
88 ns
T
TX-IDLE-TO-DIFF-
DATA
Maximum time to transition from valid idle to diff data 8 8 ns
T
TX-SKEW
Transmitter data skew between any 2 lanes 1.3 1.3 ns
T
MIN-PULSED
Minimum Instantaneous Lone Pulse Width NA 0.9 UI
T
TX-HF-DJ-DD
Transmitter Deterministic Jitter > 1.5MHz Bandwidth NA 0.15 UI
T
RF-MISMATCH
Rise/Fall Time Differential Mismatch NA 0.1 UI
PCIe Receive
UI Unit Interval 399.88 400 400.12 199.94 200.06 ps
T
RX-EYE (with jitter)
Minimum Receiver Eye Width (jitter tolerance) 0.4 0.4 UI
T
RX-EYE-MEDIUM TO
MAX JITTER
Max time between jitter median & max deviation 0.3 UI
T
RX-SKEW
Lane to lane input skew 20 8 ns
T
RX-HF-RMS
1.5 — 100 MHz RMS jitter (common clock) NA 3.4 ps
T
RX-HF-DJ-DD
Maximum tolerable DJ by the receiver (common clock) NA 88 ps
T
RX-LF-RMS
10 KHz to 1.5 MHz RMS jitter (common clock) NA 4.2 ps
T
RX-MIN-PULSE
Minimum receiver instantaneous eye width NA 0.6 UI
1.
Minimum, Typical, and Maximum values meet the requirements under PCI Express Base Specification 2.1.
Signal Symbol
Reference
Edge
Min Max Unit
Timing
Diagram
Reference
GPIO
GPIO[8:0]
1
1.
GPIO signals must meet the setup and hold times if they are synchronous or the minimum pulse width if they
are asynchronous.
Tpw_13b
2
2.
The values for this symbol were determined by calculation, not by testing.
None 50 ns See Figure 4.
Table 13 GPIO AC Timing Characteristics
Parameter Description
Gen 1 Gen 2
Units
Min
1
Typ
1
Max
1
Min
1
Typ
1
Max
1
Table 12 PCIe AC Timing Characteristics (Part 2 of 2)

89H24NT24G2ZCHLGI

Mfr. #:
Manufacturer:
IDT
Description:
PCI Interface IC PCIE SWITCH
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union