71V546S100PFGI8 Datasheet 71V546S100PFG, 71V546S133PFGI, 71V546S100PFGI | P1-P3

OCTOBER 2008

DSC-3821/05

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.

Pin Description Summary

Description

The IDT71V546 is a 3.3V high-speed 4,718,592-bit (4.5 Megabit)

synchronous SRAM organized as 128K x 36 bits. It is designed to

eliminate dead bus cycles when turning the bus around between reads

and writes, or writes and reads. Thus it has been given the name ZBT

or Zero Bus Turn-around.

Address and control signals are applied to the SRAM during one

Features

◆◆

◆

128K x 36 memory configuration, pipelined outputs

◆◆

◆

Supports high performance system speed - 133 MHz

(4.2 ns Clock-to-Data Access)

◆◆

◆

ZBT

Feature - No dead cycles between write and read

cycles

◆◆

◆

Internally synchronized registered outputs eliminate the

need to control OE

◆◆

◆

Single R/W (READ/WRITE) control pin

◆◆

◆

Positive clock-edge triggered address, data, and control

signal registers for fully pipelined applications

◆◆

◆

4-word burst capability (interleaved or linear)

◆◆

◆

Individual byte write (BW1 - BW4) control (May tie active)

◆◆

◆

Three chip enables for simple depth expansion

◆◆

◆

Single 3.3V power supply (±5%)

◆◆

◆

Packaged in a JEDEC standard 100-pin TQFP package

clock cycle, and two cycles later its associated data cycle occurs, be it

read or write.

The IDT71V546 contains data I/O, address and control signal regis-

ters. Output enable is the only asynchronous signal and can be used to

disable the outputs at any given time.

A Clock Enable (CEN) pin allows operation of the IDT71V546 to be

suspended as long as necessary. All synchronous inputs are ignored

when CEN is high and the internal device registers will hold their previous

values.

There are three chip enable pins (CE1, CE2, CE2) that allow the user

to deselect the device when desired. If any one of these three is not active

when ADV/LD is low, no new memory operation can be initiated and any

burst that was in progress is stopped. However, any pending data

transfers (reads or writes) will be completed. The data bus will tri-state two

cycles after the chip is deselected or a write initiated.

The IDT71V546 has an on-chip burst counter. In the burst mode, the

IDT71V546 can provide four cycles of data for a single address presented

to the SRAM. The order of the burst sequence is defined by the LBO input

pin. The LBO pin selects between linear and interleaved burst sequence.

The ADV/LD signal is used to load a new external address (ADV/LD =

LOW) or increment the internal burst counter (ADV/LD = HIGH).

The IDT71V546 SRAM utilizes IDT's high-performance, high-volume

3.3V CMOS process, and is packaged in a JEDEC standard 14mm x

20mm 100- pin thin plastic quad flatpack (TQFP) for high board density.

IDT71V546S/XS128K x 36, 3.3V Synchronous

SRAM with ZBT

™™

™ Feature,

Burst Counter and Pipelined Outputs

- A

Address Inputs Input Synchronous

, CE

Three Chip Enables Input Synchronous

Output Enable Input Asynchronous

R/W Read/Write Signal Input Synchronous

CEN

Clock Enable Input Synchronous

, BW

Individual Byte Write Selects Input Synchronous

CLK Clock Input N/A

ADV/LD Advance Burst Address / Load New Address Input Synchronous

LBO

Linear / Interleaved Burst Order Input Static

I/O

- I/O

, I/O

- I/O

Data Input/Output I/O Synchronous

3.3V Power Supply Static

Ground Supply Static

3821 tbl 01

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT

™™

™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol Pin Function I/O Active Description

- A

Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a

combination of the rising edge of CLK and ADV/LD Low, CEN Low and true

chip enables.

ADV/LD

Address/Load I N/A ADV/LD is a synchronous input that is used to load the internal registers with

new address and control when it is sampled low at the rising edge of clock with

the chip selected. When ADV/LD is low with the chip deselected, any burst in

progress is terminated. When ADV/LD is sampled high then the internal burst

counter is advanced for any burst that was in progress. The external addresses

are ignored when ADV/LD is sampled high.

R/W

Read/Write I N/A R/W signal is a synchronous input that identified whether the current load cycle

initiated is a Read or Write access to the memory array. The data bus activity for

the current cycle takes place two clock cycles later.

CEN

Clock Enable I LOW Synchronous Clock Enable Input. When CEN is sampled high, all other

synchronous inputs, including clock are ignored and outputs remain unchanged.

The effect of CEN sampled high on the device outputs is as if the low to high

clock transition did not occur. For normal operation, CEN must be sampled low

at rising edge of clock.

- BW

Individual Byte

Write Enables

I LOW Synchronous byte write enables. Enable 9-bit byte has its own active low byte

write enable. On load write cycles (When R/W and ADV/LD are sampled low)

the appropriate byte write signal (BW

- BW

) must be valid. The byte write

signal must also be valid on each cycle of a burst write. Byte Write signals are

ignored when R/W is sampled high. The appropriate byte(s) of data are written

into the device two cycles later. BW

- BW

can all be tied low if always doing

write to the entire 36-bit word.

, CE

Chip Enables I LOW Synchronous active low chip enable. CE

and CE

are used with CE

enable the IDT71V546. (CE

or CE

sampled high or CE

sampled low) and

ADV/LD low at the rising edge of clock, initiates a deselect cycle. the ZBT

has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after

deselect is initiated.

CE2 Chip Enable I HIGH Synchronout active high chip enable. CE

is used with CE

and CE

to enable

the chip. CE

has inverted polarity but otherwise identical to CE

and CE

CLK Clock I N/A This is the clock input to the IDT71V546. Except for OE, all timing references for

the device are made with respect to the rising edge of CLK.

I/O

- I/O

I/O

P1 -

I/O

Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data

output path are registered and triggered by the rising edge of CLK.

LBO

Linear Burst

Order

I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is

selected. When LBO is low the Linear burst sequence is selected. LBO is a

static DC input.

Output Enable I LOW Asynchronous output enable. OE must be low to read data from the 71V546.

When OE is high the I/O pins are in a high-impedance state. OE does not need

to be actively controlled for read and write cycles. In normal operation, OE can

be tied low.

Power Supply N/A N/A 3.3V power supply input.

Ground N/A N/A Ground pin.

3821 tbl 02

6.42

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT



 Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges

Functional Block Diagram

Clk

Address A [0:16]

Control Logic

Address

Control

DI DO

Input R

egister

3821 drw 01

Clock

Data I/O [0:31], I/O P[1:4]

Clk

Output Register

Mux

Sel

Gate

,CE

, CE

CEN

ADV/

BWx

LBO

128K x 36 BIT

MEMORY ARRAY

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

71V546S100PFGI8

Mfr. #:

Buy 71V546S100PFGI8

Manufacturer:

IDT

Description:

SRAM 128Kx36 ZBT SYNC 3.3V PIPELINED SRAM

Lifecycle:

New from this manufacturer.

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71V546S100PFGI8

71V546S100PFGI8

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