16
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT
™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles
(1,2,3,4,5)
NOTES:
1. D (A
1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence
of the base address A
2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE
2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address
and control are loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information
comes in two cycles before the actual data is presented to the SRAM.
t
H
E
t
S
E
R
/
W
A
1
A
2
C
L
K
C
E
N
A
D
V
/
L
D
A
D
D
R
E
S
S
O
E
D
A
T
A
I
n
t
H
D
t
S
D
t
C
H
t
C
L
t
C
Y
C
t
H
A
D
V
t
S
A
D
V
t
H
W
t
S
W
t
H
A
t
S
A
t
H
C
t
S
C
B
u
r
s
t
P
i
p
e
l
i
n
e
W
r
i
t
e
P
i
p
e
l
i
n
e
W
r
i
t
e
P
i
p
e
l
i
n
e
W
r
i
t
e
t
H
B
t
S
B
(
B
u
r
s
t
W
r
a
p
s
a
r
o
u
n
d
t
o
i
n
i
t
i
a
l
s
t
a
t
e
)
t
H
D
t
S
D
(
C
E
N
h
i
g
h
,
e
l
i
m
i
n
a
t
e
s
c
u
r
r
e
n
t
L
-
H
c
l
o
c
k
e
d
g
e
)
C
E
1
,
C
E
2
(
2
)
D
(
A
2
+
1
)
D
(
A
2
+
2
)
D
(
A
2
+
3
)
D
(
A
1
)
D
(
A
2
)
D
(
A
2
)
3
8
2
1
d
r
w
0
7
B
W
1
,
B
W
4
.
