12
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT
™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Read Operation With Chip Enable Used
(1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation With Chip Enable Used
(1)
Cycle Address R/W ADV/LD
CE
(1 )
CEN BWx OE
I/O Comments
n X X L H L X X ? Deselected
n+1 X X L H L X X ? Deselected
n+2 A0 H L L L X X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP
n+4 A1 H L L L X L Q0 Address A0 read out. Load A1
n+5 X X L H L X X Z Deselected or STOP
n+6 X X L H L X L Q1 Address A1 Read out. Deselected
n+7 A2 H L L L X X Z Address and Control meet setup
n+8 X X L H L X X Z Deselected or STOP
n+9 X X L H L X L Q2 Address A2 read out. Deselected
3821 tbl 18
Cycle Address R/W ADV/LD
CE
(1)
CEN BWx OE
I/O Comments
n X X L H L X X ? Deselected
n+1 X X L H L X X ? Deselected
n+2 A0 L L L L L X Z Address and Control meet setup
n+3 X X L H L X X Z Deselected or STOP
n+4 A1 L L L L L X D0 Address D0 Write In. Load A1
n+5 X X L H L X X Z Deselected or STOP
n+6 X X L H L X X D1 Address D1 Write In. Deselected
n+7 A2 L L L L L X Z Address and Control meet setup
n+8 X X L H L X X Z Deselected or STOP
n+9 X X L H L X X D2 Address D2 Write In. Deselected
3821 tbl 19
