71V546S100PFGI8 Datasheet 71V546S100PFG, 71V546S133PFGI, 71V546S100PFGI | P7-P9

6.42

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT

™™

™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges

Functional Timing Diagram

(1)

NOTE:

1. This assumes CEN, CE1, CE2, CE2 are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data

delay from the rising edge of clock.

A37

C37

D/Q35

n+29

A29

C29

D/Q27

ADDRESS

(A0 - A16)

CONTROL

(R/W, ADV/LD, BWx)

DATA

I/O [0:31], I/O P[1:4]

CYCLE

CLOCK

n+30

A30

C30

D/Q28

n+31

A31

C31

D/Q29

n+32

A32

C32

D/Q30

n+33

A33

C33

D/Q31

n+34

A34

C34

D/Q32

n+35

A35

C35

D/Q33

n+36

A36

C36

D/Q34

(2)

3821 drw 03

n+37

A37

C37

D/Q35

Interleaved Burst Sequence Table (LBO=VDD)

Linear Burst Sequence Table (LBO=V

SS)

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

Sequence 1 Sequence 2 Sequence 3 Sequence 4

A1 A0 A1 A0 A1 A0 A1 A0

First Address 0 0 0 1 1 0 1 1

Second Address 0 1 0 0 1 1 1 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address

(1 )

11 10 01 00

3821 tbl 09

NOTE:

1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

Sequence 1 Sequence 2 Sequence 3 Sequence 4

A1 A0 A1 A0 A1 A0 A1 A0

First Address 0 0 0 1 1 0 1 1

Second Address 0 1 1 0 1 1 0 0

Third Address 1 0 1 1 0 0 0 1

Fourth Address

(1 )

11 00 01 10

3821 tbl 10

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT

™™

™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges

Device Operation - Showing Mixed Load,

Burst, Deselect and NOOP Cycles

(2)

NOTES:

1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

2. H = High; L = Low; X = Don’t Care; Z = High Impedance.

Cycle Address R/W ADV/LD

(1 )

CEN BWx OE

I/O Comments

n A0 H L L L X X X Load read

n+1 X X H X L X X X Burst read

n+2 A1 H L L L X L Q0 Load read

n+3 X X L H L X L Q

0+1

Deselect or STOP

n+4 X X H XLXLQ1NOOP

n+5 A2 H L L L X X Z Load read

n+6 X X H X L X X Z Burst read

n+7 X X L H L X L Q2 Deselect or STOP

n+8 A3 L L LLLLQ

2+1

Load write

n+9 X X H X L L X Z Burst write

n+10 A4 L L L L L X D3 Load write

n+11 X X L H L X X D

3+1

Deselect or STOP

n+12 X X H X L X X D4 NOOP

n+13 A5 L L L L L X Z Load write

n+14 A6 H L L L X X Z Load read

n+15 A7 L L L L L X D5 Load write

n+16 X X H X L L L Q6 Burst write

n+17 A8 H L L L X X D7 Load read

n+18 X X H X L X X D

7+1

Burst read

n+19 A9 L L LLLLQ8Load write

3821 tbl 11

6.42

IDT71V546, 128K x 36, 3.3V Synchronous SRAM with

ZBT

™™

™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges

Read Operation

(1)

NOTE:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance..

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Burst Read Operation

(1)

NOTE:

1. H = High; L = Low; X = Don’t Care; Z = High Impedance.

2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.

Cycle Address R/W ADV/LD

(2)

CEN BWx OE

I/O Comments

n A0 H L L L X X X Address and Control meet setup

n+1 X X X XLXXXClock Setup Valid

n+2 X X X X X X L Q0 Contents of Address A0 Read Out

3821 tbl 12

Cycle Address R/W ADV/LD

(2 )

CEN BWx OE

I/O Comments

n A0 H L L L X X X Address and Control meet setup

n+1 X X H X L X X X Clock Setup Valid, Advance Counter

n+2 X X H X L X L Q0 Address A0 Read Out, Inc. Count

n+3 X X H XLXLQ

0+1

Address A

0+1

Read Out, Inc. Count

n+4 X X H XLXLQ

0+2

Address A

0+2

Read Out, Inc. Count

n+5 A1 H L L L X L Q

0+3

Address A

0+3

Read Out, Load A1

n+6 X X H X L X L Q0 Address A0 Read Out, Inc. Count

n+7 X X H X L X L Q1 Address A1 Read Out, Inc. Count

n+8 A2 H L L L X L Q

1+1

Address A

1+1

Read Out, Load A2

3821 tbl 13

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

71V546S100PFGI8

Mfr. #:

Buy 71V546S100PFGI8

Manufacturer:

IDT

Description:

SRAM 128Kx36 ZBT SYNC 3.3V PIPELINED SRAM

Lifecycle:

New from this manufacturer.

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71V546S100PFGI8

71V546S100PFGI8

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