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71V546S100PFGI8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
4
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT
™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Configuration — 128K X 36
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
C
E
1
C
E
2
B
W
4
B
W
3
B
W
2
B
W
1
C
E
2
V
D
D
V
S
S
C
L
K
R
/
W
C
E
N
O
E
A
D
V
/
L
D
N
C
(
2
)
N
C
(
2
)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
N
C
L
B
O
A
1
4
A
1
3
A
1
2
A
1
1
A
1
0
V
D
D
V
S
S
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DD
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DD
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DD
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DD
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DD
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DD
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DD
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DD
I/O
1
I/O
0
PK100-1
3821 drw 02
V
DD
(1)
I/O
15
I/O
P3
V
DD
I/O
P4
A
1
5
A
1
6
I/O
P1
V
DD
I/O
P2
V
SS
.
.
N
C
N
C
N
C
NOTES:
1. Pin 14 does not have to be connected directly to VDD as long as the input voltage is > VIH.
2. Pins 83 and 84 are reserved for future A17 (8M) and A18 (16M) respectively.
100 100
100 100
100
TT
TT
T
QFPQFP
QFPQFP
QFP
TT
TT
T
op op
op op
op
VV
VV
V
ieie
ieie
ie
ww
ww
w
6.42
5
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT
™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
100 TQFP Capacitance
(TA = +25°C, f = 1.0MHz, TQFP package)
Symbol Rating
Commercial &
Industrial Values
Unit
V
TERM
(2)
Terminal Voltage
with Respect to GND
-0.5 to +4.6 V
V
TERM
(3)
Terminal Voltage
with Respect to GND
-0.5 to V
DD
+0.5 V
T
A
(4)
Commercial
Operating Ambient
Temperature
0 to +70
o
C
Industrial
Operating Ambient
Temperature
-40 to +85
o
C
T
BIAS
Temperature Under Bias -55 to +125
o
C
T
STG
Storage Temperature -55 to +125
o
C
P
T
Power Dissipation 2.0 W
I
OUT
DC Output Current 50 mA
3821 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
2. VDD and Input terminals only.
3. I/O terminals.
4. During production testing, the case temperature equals the ambient temperature.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol Parameter
(1 )
Conditions Max. Unit
C
IN Input Capacitance VIN = 3dV 5 pF
C
I/O I/O Capacitance VOUT = 3dV 7 pF
3821 tbl 06
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Grade
Ambient
Temperature
(1)
V
SS
V
DD
Commercial 0
O
C to +70
O
C0V 3.3V±5%
Industrial -40
O
C to +85
O
C0V 3.3V±5%
3821 tbl 03
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
3. VDD needs to be ramped up smoothly to the operating level. If there are any
glitches on VDD that cause the voltage level to drop below 2.0 volts then the
device needs to be reset by holding VDD to 0.0 volts for a minimum of 100 ms.
Symbol Parameter Min. Typ. Max. Unit
V
DD
(3)
Supply Voltage 3.135 3.3 3.465 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage - Inputs 2.0
____
4.6 V
V
IH
Input High Voltage - I/O 2.0
____
V
DD
+0.3
(2)
V
V
IL
Input Low Voltage -0.5
(1)
____
0.8 V
3821 tbl 04
NOTES:
1. During production testing, the case temperature equals the ambient temperature.
6
IDT71V546, 128K x 36, 3.3V Synchronous SRAM with
ZBT
™™
™™
™ Feature, Burst Counter and Pipelined Outputs Commercial and Industrial Temperature Ranges
Synchronous Truth Table
(1)
Partial Truth Table for Writes
(1)
NOTES:
1. L = V
IL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE
1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE
1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if either one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
CEN
R/W Chip
(5 )
Enable
ADV/LD
BWx
ADDRESS
USED
PREVIOUIS CYCLE CURRENT CYCLE I/O
(2 cycles later)
L L Select L Valid External X LOAD WRITE D
(7)
L H Select L X External X LOAD READ Q
(7 )
L X X H Valid Internal LOAD WRITE/
BURST WRITE
BURST WRITE
(Advance Burst Counter)
(2)
D
(7)
L X X H X Internal LOAD READ/
BURST READ
BURST READ
(Advance Burst Counter)
(2)
Q
(7 )
L X Deselect L X X X DESELECT or STOP
(3 )
HiZ
L X X H X X DESELECT / NOOP NOOP HiZ
H X X X X X X SUSPEND
(4 )
Previous Value
3821 tbl 07
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
Operation R/W
BW
1
BW
2
BW
3
BW
4
READ H X X X X
WRITE ALL BYTES L L L L L
WRITE BYTE 1 (I/O [0:7], I/O
P1
)
(2)
LLHHH
WRITE BYTE 2 (I/O [8:15], I/O
P2
)
(2 )
LHLHH
WRITE BYTE 3 (I/O [16:23], I/O
P3
)
(2)
LHHLH
WRITE BYTE 4 (I/O [24:31], I/O
P4
)
(2)
LHHHL
NO WRITE LHHHH
3821 tbl 08
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

71V546S100PFGI8

Mfr. #:
Buy 71V546S100PFGI8
Manufacturer:
IDT
Description:
SRAM 128Kx36 ZBT SYNC 3.3V PIPELINED SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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