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MT8LSDT3264HG-133D2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
64MB, 128MB, 256MB (x64, DR)
144-PIN SDRAM SODIMM
09005aef8077d63a Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
10 ©2004 Micron Technology, Inc. All rights reserved.
Commands
The Truth Table provides a quick reference of avail-
able commands. This is followed by written descrip-
tion of each command. For a more detailed des-
cription of commands and operations, refer to the
64Mb, 128Mb, or 256Mb SDRAM component data
sheet.
NOTE:
1. A0–A11 (64MB and 128MB) , or A0–A12 (256MB) provide device row address, and BA0, BA1 determine which device
bank is made active.
2. A0–A7 (64MB) or A0–A8 (128MB and 256MB) provide device column address; A10 HIGH enables the auto precharge fea-
ture (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is
being read from or written to.
3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and
BA0, BA1 are “Don’t Care.”
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
6. A0–A11 define the op-code written to the mode register; for 64MB and 128MB, A12 should be driven low.
7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock delay).
Table 9: Truth Table – SDRAM Commands and DQMB Operation
CKE is HIGH for all commands shown except SELF REFRESH
NAME (FUNCTION) CS# RAS# CAS# WE# DQMB ADDR DQ NOTES
COMMAND INHIBIT (NOP)
HX XX X X X
NO OPERATION (NOP)
LHHHX X X
ACTIVE (Select bank and activate row)
L L H H X Bank/Row X 1
READ (Select bank and column, and start READ burst)
LHLH
L/H
8
Bank/Col X 2
WRITE (Select bank and column, and start WRITE burst)
LHLL
L/H
8
Bank/Col Valid 2
BURST TERMINATE
LHHL X X Active
PRECHARGE (Deactivate row in bank or banks)
LLHLX Code X 3
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LL LHX X X 4, 5
LOAD MODE REGISTER
LL LLXOp-codeX 6
Write Enable/Output Enable
–– –– L – Active7
Write Inhibit/Output High-Z
– – – – H – High-Z 7
64MB, 128MB, 256MB (x64, DR)
144-PIN SDRAM SODIMM
09005aef8077d63a Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
11 ©2004 Micron Technology, Inc. All rights reserved.
Absolute Maximum Ratings
Stresses greater than those listed may cause perma-
nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Voltage on V
DD Supply
Relative to Vss . . . . . . . . . . . . . . . . . . . .-1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to Vss . . . . . . . . . . . . . . . . . . . .-1V to +4.6V
Operating Temperature
T
OPR
(Commercial - ambient) . . . . . .0°C to +65°C
T
OPR
(Industrial - ambient). . . . . .. -40°C to +85°C
Storage Temperature (plastic) . . . . . .-55°C to +150°C
NOTE:
a. Value calculated as one module rank in this operating condition, and all other module ranks in power-down mode.
b. Value calculated reflects all module ranks in this operating condition.
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1, 5, 6; notes appear on page 15; VDD, VDDQ = +3.3V ±0.3V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
SUPPLY VOLTAGE
V
DD, VDDQ3 3.6 V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH 2VDD + 0.3 V 22
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL -0.3 0.8 V 22
INPUT LEAKAGE CURRENT:
Any input 0V ≤ V
IN ≤ VDD
(All other pins not under test = 0V)
Command and
Address Inputs
II
-40 40 µA
33
CK, S#
-20 20 µA
DQMB
-5 5 µA
OUTPUT LEAKAGE CURRENT: DQ pins are
disabled; 0V ≤ V
OUT ≤ VDDQ
DQ
IOZ -5 5 µA 33
OUTPUT LEVELS:
Output High Voltage (I
OUT = -4mA)
Output Low Voltage (I
OUT = 4mA)
V
OH 2.4 – V
V
OL –0.4 V
Table 11: IDD Specifications and Conditions – 64MB
Notes: 1, 1, 5, 6, 11, 13; notes appear on page 15; VDD, VDDQ = +3.3V ±0.3V; DRAM components only
MAX
PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES
OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE;
t
RC
=
t
RC (MIN)
I
DD1
a
508 468 388 mA 3, 18, 19,
29
STANDBY CURRENT: Power-Down Mode; All device device banks
idle; CKE = LOW
IDD2
b
16 16 16 mA 29
STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All
device banks active after
t
RCD met; No accesses in progress
I
DD3
a
188 188 148 mA 3, 12, 19,
29
OPERATING CURRENT: Burst Mode; Continuous burst; READ or
WRITE; All device banks active
I
DD4
a
608 568 488 mA 3, 18, 19,
29
AUTO REFRESH CURRENT
t
RFC =
t
RFC (MIN)
IDD5
b
1,840 1,680 1,520 mA 3, 12, 18,
19, 29,30
CKE = HIGH; S# = HIGH
t
RFC = 15.625µs
IDD6
b
24 24 24 mA
SELF REFRESH CURRENT: CKE ≤ 0.2V
(Low power not available with industrial
temperature option)
Standard
I
DD7
b
8 88mA 4
Low Power (L)
I
DD7
b
4 44mA
64MB, 128MB, 256MB (x64, DR)
144-PIN SDRAM SODIMM
09005aef8077d63a Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
12 ©2004 Micron Technology, Inc. All rights reserved.
NOTE:
a. Value calculated as one module bank in this operating condition, and all other module banks in power-down mode.
b. Value calculated reflects all module banks in this operating condition.
NOTE:
a. Value calculated as one module bank in this operating condition, and all other module banks in power-down mode.
b. Value calculated reflects all module banks in this operating condition.
Table 12: IDD Specifications and Conditions – 128MB
Notes: 1, 1, 5, 6, 11, 13; notes appear on page 15; VDD, VDDQ = +3.3V ±0.3V; DRAM components only
MAX
PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES
OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE;
t
RC
=
t
RC (MIN)
I
DD1
a
648 608 568 mA 3, 18, 19,
29
STANDBY CURRENT: Power-Down Mode; All device device banks
idle; CKE = LOW
I
DD2
b
16 16 16 mA 29
STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All
device banks active after
t
RCD met; No accesses in progress
I
DD3
a
208 208 168 mA 3, 12, 19,
29
OPERATING CURRENT: Burst Mode; Continuous burst; READ or
WRITE; All device banks active
IDD4
a
668 608 568 mA 3, 18, 19,
29
AUTO REFRESH CURRENT
t
RFC =
t
RFC (MIN)
I
DD5
b
2,640 2,480 2,160 mA 3, 12, 18,
19, 29, 30
CKE = HIGH; S# = HIGH
t
RFC = 15.625µs
I
DD6
b
24 24 24 mA
SELF REFRESH CURRENT: CKE ≤ 0.2V
(Low power not available with industrial
temperature option)
Standard
I
DD7
b
16 16 16 mA 4
Low Power (L)
I
DD7
b
888mA
Table 13: IDD Specifications and Conditions – 256MB
Notes: 1, 1, 5, 6, 11, 13; notes appear on page 15; VDD, VDDQ = +3.3V ±0.3V; DRAM components only
MAX
PARAMETER/CONDITION SYMBOL -13E -133 -10E UNITS NOTES
OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE;
t
RC
=
t
RC (MIN)
IDD1
a
548 508 508 mA 3, 18, 19,
29
STANDBY CURRENT: Power-Down Mode; All device device banks
idle; CKE = LOW
I
DD2
b
16 16 16 mA 29
STANDBY CURRENT: Active Mode;
CKE = HIGH; CS# = HIGH; All device banks active after
t
RCD met;
No accesses in progress
IDD3
a
168 168 168 mA 3, 12, 19,
29
OPERATING CURRENT: Burst Mode; Continuous burst; READ or
WRITE; All device banks active
I
DD4
a
548 548 548 mA 3, 18, 19,
29
AUTO REFRESH CURRENT
t
RFC =
t
RFC (MIN)
I
DD5
b
2,280 2,160 2,160 mA 3, 12, 18,
19, 29, 30
CKE = HIGH; S# = HIGH
t
RFC = 7.8125µs
I
DD6
b
28 28 28 mA
SELF REFRESH CURRENT: CKE ≤ 0.2V
(Low power not available with industrial
temperature option)
Standard
I
DD7
b
20 20 20 mA 4
Low Power (L)
I
DD7
b
12 12 12 mA
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

MT8LSDT3264HG-133D2

Mfr. #:
Buy MT8LSDT3264HG-133D2
Manufacturer:
Micron
Description:
MODULE SDRAM 256MB 144SODIMM
Lifecycle:
New from this manufacturer.
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