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MT8LSDT3264HG-133D2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
64MB, 128MB, 256MB (x64, DR)
144-PIN SDRAM SODIMM
09005aef8077d63a Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
13 ©2004 Micron Technology, Inc. All rights reserved.
Table 14: Capacitance
Notes 1, 2; notes appear on page 15
PARAMETER SYMBOL MIN MAX UNITS
Input Capacitance: Address and Command
C
I1 20 28 pF
Input Capacitance: CK, CKE, S#
C
I2 10 14 pF
Input Capacitance: DQMB
C
I4 57pF
Inuput/Output Capacitnance: DQ
C
IO 812pF
Table 15: Electrical Characteristics and Recommended AC Operating Conditions
Notes: 5, 6, 8, 9, 11, 31; notes appear on page 15
Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters
AC CHARACTERISTICS -13E -133 -10E
UNITS NOTESPARAMETER SYMBOL MIN MAX MIN MAX MIN MAX
Access time from CLK
(positive edge)
CL = 3
t
AC(3) 5.4 5.4 6 ns 27
CL = 2
t
AC(2) 5.4 6 6 ns
Address hold time
t
AH 0.8 0.8 1 ns
Address setup time
t
AS 1.5 1.5 2 ns
CLK high-level width
t
CH 2.5 2.5 3 ns
CLK low-level width
t
CL 2.5 2.5 3 ns
Clock cycle time CL = 3
t
CK(3) 7 7.5 8 ns 24
CL = 2
t
CK(2) 7.5 10 10 ns 24
CKE hold time
t
CKH 0.8 0.8 1 ns
CKE setup time
t
CKS 1.5 1.5 2 ns
CS#, RAS#, CAS#, WE#, DQM hold time
t
CMH 0.8 0.8 1 ns
CS#, RAS#, CAS#, WE#, DQM setup time
t
CMS 1.5 1.5 2 ns
Data-in hold time
t
DH 0.8 0.8 1 ns
Data-in setup time
t
DS 1.5 1.5 2 ns
Data-out high-impedance time CL = 3
t
HZ(3) 5.4 5.4 6 ns 10
CL = 2
t
HZ(2) 5.4 6 6 ns 10
Data-out low-impedance time
t
LZ 1 1 1 ns
Data-out hold time (load)
t
OH 3 3 3 ns
Data-out hold time (no load)
t
OHN 1.8 1.8 1.8 ns 28
ACTIVE to PRECHARGE command
t
RAS 37 120,000 44 120,000 50 120,000 ns 32
ACTIVE to ACTIVE command period
t
RC 60 66 70 ns
ACTIVE to READ or WRITE delay
t
RCD 15 20 20 ns
Refresh period
t
REF 64 64 64 ms
AUTO REFRESH period
t
RFC666670 ns
PRECHARGE command period
t
RP 15 20 20 ns
ACTIVE bank a to ACTIVE bank b command
t
RRD 14 15 20 ns
Transition time
t
T 0.3 1.2 0.3 1.2 0.3 1.2 ns 7
WRITE recovery time
t
WR
1 CLK
+ 7ns
1 CLK +
7.5ns
1 CLK
+ 7ns
ns 24
14 15 15 ns 25
Exit SELF REFRESH to ACTIVE command
t
XSR677580 ns20
64MB, 128MB, 256MB (x64, DR)
144-PIN SDRAM SODIMM
09005aef8077d63a Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
14 ©2004 Micron Technology, Inc. All rights reserved.
Table 16: AC Functional Characteristics
Notes: 5, 6, 7, 8, 9, 11, 31; notes appear on page 15
PARAMETER SYMBOL -13E -133 -10E UNITS NOTES
READ/WRITE command to READ/WRITE command
t
CCD
111
t
CK
17
CKE to clock disable or power-down entry mode
t
CKED
111
t
CK
14
CKE to clock enable or power-down exit setup mode
t
PED
111
t
CK
14
DQM to input data delay
t
DQD
000
t
CK
17
DQM to data mask during WRITEs
t
DQM
000
t
CK
17
DQM to data high-impedance during READs
t
DQZ
222
t
CK
17
WRITE command to input data delay
t
DWD
000
t
CK
17
Data-in to ACTIVE command
t
DAL
454
t
CK
15, 21
Data-in to PRECHARGE command
t
DPL
222
t
CK
16, 21
Last data-in to burst STOP command
t
BDL
111
t
CK
17
Last data-in to new READ/WRITE command
t
CDL
111
t
CK
17
Last data-in to PRECHARGE command
t
RDL
222
t
CK
16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH command
t
MRD
222
t
CK
26
Data-out to high-impedance from PRECHARGE
command
CL = 3
t
ROH(3)
333
t
CK
17
CL = 2
t
ROH(2)
222
t
CK
17
64MB, 128MB, 256MB (x64, DR)
144-PIN SDRAM SODIMM
09005aef8077d63a Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
15 ©2004 Micron Technology, Inc. All rights reserved.
Notes
1. All voltages referenced to VSS.
2. This parameter is sampled. V
DD, VDDQ = +3.3V;
f= 1 MHz; T
A
= 25°C; pin under test biased at
1.4V.
3. I
DD is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range is ensured (Com-
mercial temperature: 0°C ≤ T
A
≤ +70°C and Indus-
trial Temperature: -40°C ≤ T
A
≤ +85°C).
6. An initial pause of 100µs is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
DD
and VDDQ must be powered up simultaneously.
V
SS and VSSQ must be at the same potential.) The
two AUTO REFRESH command wake-ups should
be repeated any time the
t
REF refresh require-
ment is exceeded.
7. AC characteristics assume
t
T = 1ns.
8. In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between
V
IH and VIL (or between VIL and VIH) in a mono-
tonic manner.
9. Outputs measured at 1.5V with equivalent load:
10.
t
HZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
V
OH or VOL. The last valid data element will meet
t
OH before going High-Z.
11. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V,
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at V
IL
(MAX) and V
IH
(MIN)
and no longer at the 1.5V crossover point.
12. Other input signals are allowed to transition no
more than once every two clocks and are other-
wise at valid V
IH or VIL levels.
13. IDD specifications are tested after the device is
properly initialized.
14. Timing actually specified by
t
CKS; clock(s) speci-
fied as a reference only at minimum cycle rate.
15. Timing actually specified by
t
WR plus
t
RP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by
t
WR.
17. Required clocks are specified by JEDEC functionality
and are not dependent on any timing parameter.
18. The IDD current will increase or decrease propor-
tionally according to the amount of frequency
alteration for the test condition.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times
during this period.
21. Based on
t
CK = 10ns for -10E, and
t
CK = 7.5ns for
-133 and -13E.
22. V
IH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width ≤ 3ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL under-
shoot: V
IL (MIN) = -2V for a pulse width ≤ 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing
t
WR, and PRECHARGE commands). CKE may
be used to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (
t
RP) begins 7ns for -13E; 7.5ns for -133
and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
t
AC for -133/-13E at CL = 3 with no load is 4.6ns
and is guaranteed by design.
28. Parameter guaranteed by design.
29. For -13E, CL = 2 and
t
CK = 7.5ns; for -133, CL = 3
and
t
CK = 7.5ns; for -10E, CL= 2 and
t
CK = 10ns.
30. CKE is HIGH during refresh command period
t
RFC
(MIN) else CKE is LOW. The I
DD
6 limit is actually a
nominal value and does not result in a fail value.
31. Refer to component datasheet for timing wavfe-
forms.
32. The value of
t
RAS used in -13E speed grade mod-
ule SPDs is calculated from
t
RC -
t
RP = 45ns.
33. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
Q
50pF
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

MT8LSDT3264HG-133D2

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MODULE SDRAM 256MB 144SODIMM
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