64MB, 128MB, 256MB (x64, DR)
144-PIN SDRAM SODIMM
09005aef8077d63a Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
7 ©2004 Micron Technology, Inc. All rights reserved.
Mode register bits M0–M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4–M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. For 64MB and 128MB, Address A12 (M12) is unde-
fined but should be driven LOW during loading of the
mode register.
The mode register must be loaded when all device
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst ori-
ented, with the burst length being programmable, as
shown in Figure 4, Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 1, 2, 4, or 8
locations are available for both the sequential and the
interleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in Table 7,
Burst Definition Table, on page 8. The block is
uniquely selected by A1–Ai when the burst length is set
to two; by A2–Ai when the burst length is set to four;
and by A3–Ai when the burst length is set to eight. See
Note 8 of Table 7, Burst Definition Table, on page 8 for
Ai values. The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. Full-page bursts wrap within the page if the
boundary is reached, as shown in Table 7, Burst Defini-
tion Table, on page 8.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in Table 7, Burst
Definition Table, on page 8.
Figure 4: Mode Register Definition
Diagram
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
256MB Module
64MB Module and 128MB Module
M0
0
1
0
1
0
1
0
1
Burst LengthCAS Latency BT
A9
A7
A6 A5 A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
654
3
8
2
1
0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Op Mode
A10
A11
10
11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M12, M11, M10 = “0, 0, 0”
to ensure compatibility
with future devices.
*Should program
M11 and M10 = “0, 0”
to ensure compatibility
with future devices.
A12
12
Burst LengthCAS Latency BT
A9
A7
A6 A5 A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
654
3
8
2
1
0
Op Mode
A10
A11
10
11
Reserved* WB
