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MT8LSDT3264HG-133D2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
64MB, 128MB, 256MB (x64, DR)
144-PIN SDRAM SODIMM
09005aef8077d63a Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
16 ©2004 Micron Technology, Inc. All rights reserved.
SPD Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Fig-
ure 6, Data Validity, and Figure 7, Definition of Start
and Stop).
SPD Start Condition
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
All communications are terminated by a stop condi-
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
SPD Acknowledge
Acknowledge is a software convention used to indi-
cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 8,
Acknowledge Response From Receiver).
The SPD device will always respond with an
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.
Figure 6: Data Validity Figure 7: Definition of Start and Stop
Figure 8: Acknowledge Response From Receiver
SCL
SDA
DATA STABLE DATA STABLEDATA
CHANGE
SCL
SDA
START
BIT
STOP
BIT
SCL from Master
Data Output
f
rom Transmitter
Data Output
f
rom Receiver
98
Acknowledge
64MB, 128MB, 256MB (x64, DR)
144-PIN SDRAM SODIMM
09005aef8077d63a Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
17 ©2004 Micron Technology, Inc. All rights reserved.
Figure 9: SPD EEPROM Timing Diagram
Table 17: EEPROM Device Select code
The most significant bit (b7) is sent first
DEVICE TYPE IDENTIFIER CHIP ENABLE RW
b7 b6 b5 b4 b3 b2 b1 b0
Memory Area Select Code (two arrays)
1010SA2SA1SA0RW
Protection Register Select Code
0110SA2SA1SA0RW
Table 18: EEPROM Operating modes
MODE RW BIT WC BYTES INITIAL SEQUENCE
Current Address Read
1V
IH or VIL 1
START, Device Select, RW
= 1
Random Address Read
0V
IH or VIL 1
START, Device Select, RW
= 0, Address
1V
IH or VIL 1
reSTART, Device Select, RW
= 1
Sequential Read
1VIH or VIL ≥ 1
Similar to Current or Random Address Read
Byte Write
0V
IL 1
START, Device Select, RW
= 0
Page Write
0VIL ≤ 16
START, Device Select, RW
= 0
SCL
SDA IN
SDA OUT
t
LOW
t
SU:STA
t
HD:STA
t
F
t
HIGH
t
R
t
BUF
t
DH
t
AA
t
SU:STO
t
SU:DAT
t
HD:DAT
UNDEFINED
64MB, 128MB, 256MB (x64, DR)
144-PIN SDRAM SODIMM
09005aef8077d63a Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD8C8_16_32x64HG.fm - Rev. C 6/04 EN
18 ©2004 Micron Technology, Inc. All rights reserved.
NOTE:
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
Table 19: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS
SUPPLY VOLTAGE
V
DD 33.6 V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH VDD x 0.7 VDD + 0.5 V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL -1 VDD x 0.3 V
OUTPUT LOW VOLTAGE: I
OUT = 3mA
V
OL –0.4 V
INPUT LEAKAGE CURRENT: V
IN = GND to VDD
ILI –10 µA
OUTPUT LEAKAGE CURRENT: V
OUT = GND to VDD
ILO –10 µA
STANDBY CURRENT:
SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V ±10%
I
SB –30 µA
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
I
CC –2 mA
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time the bus must be free before a new transition can start
t
BUF 1.3 µs
Data-out hold time
t
DH 200 ns
SDA and SCL fall time
t
F 300 ns 2
Data-in hold time
t
HD:DAT 0 µs
Start condition hold time
t
HD:STA 0.6 µs
Clock HIGH period
t
HIGH 0.6 µs
Noise suppression time constant at SCL, SDA inputs
t
I50ns
Clock LOW period
t
LOW 1.3 µs
SDA and SCL rise time
t
R0.3µs2
SCL clock frequency
f
SCL 400 KHz
Data-in setup time
t
SU:DAT 100 ns
Start condition setup time
t
SU:STA 0.6 µs 3
Stop condition setup time
t
SU:STO 0.6 µs
WRITE cycle time
t
WRC 10 ms 4
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

MT8LSDT3264HG-133D2

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Manufacturer:
Micron
Description:
MODULE SDRAM 256MB 144SODIMM
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