Watchdog/Alarm Counter
The contents of the watchdog/alarm counter, which is a
separate 24-bit down counter, are accessed in the
address range 04h–06h. When this counter is written, the
counter and a seed register are loaded with the desired
value. When the counter is to be reloaded, it uses the
value in the seed register. When the counter is read, the
current counter value is latched into a register, which is
output on the serial data line while the counter continues
to decrement.
IIf the counter is not needed, it can be disabled and
used as a 24-bit cache of NV RAM by setting the
WACE bit in the control register to logic 0. If all 24 bits
of the watchdog/alarm counter are written to zero, the
counter is disabled, independent of the WACE bit set-
ting. When the watchdog counter is is written to a
nonzero value, and WACE is written to logic 1, the func-
tion of the counter is determined by the WD/ALM bit.
When the WD/ALM bit in the control register is set to
logic 0, the WD/ALM counter decrements every second
until it reaches zero. At this point, the AF bit in the sta-
tus register is set to 1 and the counter is reloaded and
restarted. AF remains set until cleared by writing it to 0.
If AIE = 1, the INT pin goes active whenever AF = 1.
WDSTR does not affect operation when WD/ALM = 0.
When the WD/ALM bit is set to logic 1, the WD/ALM
counter decrements every 1/4096 of a second (approx-
imately every 244us) until it reaches zero. When any of
the watchdog counters bytes are read, the seed value
is reloaded and the counter restarts. Writing to the
watchdog counter updates the seed value and reloads
the counter with the new seed value. When the counter
reaches zero, the AF bit is set and the counter stops.
If WDSTR = 0, the RST pin pulses low for 250ms, and
accesses to the device are inhibited. At the end of the
250ms pulse, the AF bit is cleared to zero, the RST pin
becomes high impedance, and read/write access to
the device is enabled.
If WDSTR = 1 and the counter reaches zero, the AF bit
is set and the counter stops. If AIE = 0, AF remains set
until cleared by writing it to 0. If AIE = 1, the INT pin
pulses low for 250ms. At the end of the 250ms pulse,
the AF bit is cleared and INT becomes high impedance.
The 250ms pulse on INT or RST cannot be truncated by
writing either AF or AIE to zero during the low time. If the
INT counter is written during the 250ms pulse, the
counter starts decrementing upon the pulse completion.
The watchdog and alarm function operates from V
CC
or
V
BAT
. When the AF bit is set, INT is pulled low when the
device is powered by V
CC
or V
BAT
.
Note: WACE must be toggled from logic 0 to logic 1
after the watchdog counter is written from a zero to a
nonzero value.
Power-Up/Power-Down Reset and
Pushbutton Reset Functions
A precision temperature-compensated reference and
comparator circuit monitors the status of V
CC
. When an
out-of-tolerance condition occurs, an internal power-fail
signal is generated that forces the RST pin low and
blocks read/write access to the DS1374. When V
CC
returns to an in-tolerance condition, the RST pin is held
low for 250ms to allow the power supply to stabilize. If
the EOSC bit is set to a logic 1 (to disable the oscillator in
battery-backup mode), the reset signal is kept active for
250ms plus the startup time of the oscillator.
The DS1374 provides for a pushbutton switch to be con-
nected to the RST output pin. When the DS1374 is not in
a reset cycle, it continuously monitors the RST signal for
a low-going edge. If an edge is detected, the DS1374
debounces the switch by pulling the RST pin low and
inhibits read/write access. After the internal 250ms timer
has expired, the device continues to monitor the RST
line. If the line is still low, the DS1374 continues to moni-
tor the line, looking for a rising edge. Upon detecting
release, the DS1374 forces the RST pin low and holds it
low for an additional 250ms.
DS1374
I
2
C, 32-Bit Binary Counter Watchdog RTC with
Trickle Charger and Reset Input/Output
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