Figure 10. I
2
C Read Protocol
Accordingly, the following bus conditions have been
defined:
Bus not busy: Both data and clock lines remain
high.
Start data transfer: A change in the state of the
data line from high to low, while the clock line is
high, defines a START condition.
Stop data transfer: A change in the state of the
data line from low to high, while the clock line is
high, defines a STOP condition.
Data valid: The state of the data line represents
valid data when, after a START condition, the data
line is stable for the duration of the high period of
the clock signal. The data on the line must be
changed during the low period of the clock signal.
There is one clock pulse per bit of data.
Each data transfer is initiated with a START condi-
tion and terminated with a STOP condition. The
number of data bytes transferred between the
START and the STOP conditions is not limited, and
is determined by the master device. The informa-
tion is transferred byte-wise and each receiver
acknowledges with a ninth bit. A standard mode
(100kHz clock rate) and a fast mode (400kHz clock
rate) are defined within the I
2
C bus specifications.
Acknowledge: Each receiving device, when
addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device
must generate an extra clock pulse that is associat-
ed with this acknowledge bit.
A device that acknowledges must pull down the
SDA line during the acknowledge clock pulse in
such a way that the SDA line is stable low during
the high period of the acknowledge-related clock
pulse. Setup and hold times must be considered. A
master must signal an end of data to the slave by
not generating an acknowledge bit on the last byte
that has been clocked out of the slave. In this case,
the slave must leave the data line high to enable
the master to generate the STOP condition.
Figures 9 and 10 detail how data transfer is accom-
plished on the 2-wire bus. Depending on the state of
the R/W bit, two types of data transfer are possible:
Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the slave address. Next follows a number
of data bytes. The slave returns an acknowledge
bit after each received byte.
Data transfer from a slave transmitter to a mas-
ter receiver. The master transmits the first byte
(the slave address). The slave then returns an
acknowledge bit. Next follows a number of data
bytes transmitted by the slave to the master. The
master returns an acknowledge bit after all
received bytes other than the last byte. At the end
of the last received byte, a “not acknowledge” is
returned.
The master device generates the serial clock puls-
es and the START and STOP conditions. A transfer
is ended with a STOP condition or with a repeated
START condition. Since a repeated START condi-
tion is also the beginning of the next serial transfer,
the bus is not released.
The DS1374 can operate in the following two modes:
Slave Receiver Mode (Write Mode): Serial data
and clock data are received through SDA and SCL.
After each byte is received, an acknowledge bit is
transmitted. START and STOP conditions are rec-
ognized as the beginning and end of a serial trans-
fer. Address recognition is performed by hardware
after reception of the slave address and direction
bit. The slave address byte is the first byte
received after the master generates a START con-
dition. The slave address byte contains the 7-bit
DS1374 address, which is 1101000, followed by
the direction bit (R/W), which is zero for a write.
After receiving and decoding the slave address
byte, the DS1374 outputs an acknowledge on SDA.
