Automotive Full Bridge MOSFET Driver
A3921
10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
but not both of the PWMH and PWML inputs. Synchronous
rectification turns on the complementary MOSFET to the one that
is turned off. This ensures that the recirculating current passes
through the lower resistance conduction path, rather than the
body diode of the MOSFET.
When SR is low, synchronous rectification is disabled. In this
case, fewer MOSFET switching cycles occur, reducing dissipa-
tion in the A3921. However, load current recirculates through the
higher resistance body diode of the power MOSFETs, causing
greater power dissipation in the power bridge.
RESET Pin This is an active-low input, and when active it allows
the A3921 to enter sleep mode. When RESET is held low, the
regulator and all internal circuitry are disabled and the A3921
enters sleep mode. Before fully entering sleep mode, there is a
short delay while the regulator decoupling and storage capacitors
discharge. This typically takes a few milliseconds, depending on
the application conditions and component values.
During sleep mode, current consumption from the VBB supply
is reduced to a minimal level. In addition, latched faults and the
corresponding fault flags are cleared. When the A3921 is coming
out of sleep mode, the protection logic ensures that the gate drive
outputs are off until the charge pump reaches its correct operat-
ing condition. The charge pump stabilizes in approximately 3 ms
under nominal conditions.
RESET can be used also to clear latched fault flags without
entering sleep mode. To do so, hold RESET low for less then the
reset pulse time, t
RES
. This clears any latched fault that disables
the outputs, such as short circuit detection or bootstrap capacitor
undervoltage.
Note that the A3921 can be configured to start without any exter-
nal logic input. To do so, pull up the RESET pin to V
BB
by means
of an external resistor. The resistor value should be between
20 and 33 kΩ.
Coast and Brake States
To put the power bridge into a coast state, that is all power bridge
MOSFETs switched off, the two PWM inputs, PWMH and
PWML, must be held low and at the same time SR must be held
low. This forces all gate drive outputs low.
Braking is achieved by forcing the power bridge to apply a short
across the load, allowing the back EMF of the load to generate a
braking torque.
Several brake states are possible using combinations of inputs
on PWMH, PWML, and SR. For example, holding PWML and
SR high, while PWMH is low, turns on both low-side FETs to
short the load. The shorting path is always present and provides
braking in both directions of motor rotation. Another example is
holding SR low, when PWML is high and PWMH is low, mak-
ing only one low-side FET active, and the braking current flow
through the body diode of the opposite low-side FET. This pro-
vides braking in only one direction, because the diode does not
permit the braking current to flow if the motor is reversed. Also,
the braking current can be made to circulate around the high-side
switches by swapping PWMH and PWML.
Diagnostics
Several diagnostic features are integrated into the A3921 to
provide indication of fault conditions and, if required, take action
to prevent permanent damage. In addition to system-wide faults
such as undervoltage and overtemperature, the A3921 integrates
individual drain-source monitors for each external FET, to pro-
vide short circuit detection.
Diagnostic Management Pins
VDSTH Pin Faults on the external FETs are determined by
measuring the drain-source voltage, V
DS
, of each active FET
and comparing it to the threshold voltage applied to the VDSTH
input, V
DSTH
. To avoid false fault detection during switching
transients, the comparison is delayed by an internal blanking
timer. If the voltage applied to the VDSTH pin is greater than the
disable threshold voltage, V
DSDIS
, then FET short circuit detec-
tion is disabled.
VDRAIN Pin This is a low current sense input from the top of the
external FET bridge. This input allows accurate measurement of
the voltage at the drain of the high-side FETs. It should be con-
nected directly to the common connection point for the drains of
the power bridge FETs at the positive supply connection point.
The input current to the VDRAIN pin is proportional to the volt-
age on the VDSTH pin and can be approximated by:
I
VDRAIN
= 72 × V
DSTH
+ 52 ,
where I
VDRAIN
is the current into the VDRAIN pin, in μA, and
V
DSTH
is the voltage on the VDSTH pin, in V.
FF1 and FF2 Pins These are open drain output fault flags, which
indicate fault conditions by their state, as shown in table 3. In
