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A3921KLPTR-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Automotive Full Bridge MOSFET Driver
A3921
19
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
VDRAIN
LSS
GLB
SB
GHB
CB
NC
VREG
C
A
GH
A
S
A
GL
A
VBB
NC
VDSTH
RDEAD
FF2
FF1
RESET
PWMH
PWML
SR
V5
PHASE
NC
GND
CP1
CP2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Control Logic
Reg
Charge
Pump
t
DEAD
Reg
Pin-out Diagram
Terminal List
Number Name Description Number Name Description
1 VDRAIN High-side common drain 16 CP1 Pump capacitor
2 LSS Low-side common source 17 GND Ground
3 GLB Low-side gate drive B 18 NC No connection
4 SB Load connection B 19 PHASE Phase control input
5 GHB High-side gate drive B 20 V5 5 V regulator
6 CB Bootstrap capacitor B 21 SR SR control input
7 NC No connection 22 PWML Low-side PWM control input
8 VREG Regulated 13 V 23 PWMH High-side PWM control input
9 CA Bootstrap capacitor A 24 RESET Reset input
10 GHA High-side gate drive A 25 FF1 Fault Flag 1 output
11 SA Load connection A 26 FF2 Fault Flag 2 output
12 GLA Low-side gate drive A 27 RDEAD Dead time setting input
13 VBB Main supply 28 VDSTH V
DS
threshold level Input
14 NC No connection
–PAD
Exposed pad for enhanced thermal
dissipation (underside)
15 CP2 Pump capacitor
Automotive Full Bridge MOSFET Driver
A3921
20
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package LP 28-Pin TSSOP with Exposed Thermal Pad
1.20 MAX
0.10 MAX
C
SEATING
PLANE
C0.10
28X
6.10
0.65
0.45
1.65
3.00
3.00
5.00
5.00
0.25
0.65
21
28
GAUGE PLANE
SEATING PLANE
B
A
28
21
A
Terminal #1 mark area
B
For reference only
(reference JEDEC MO-153 AET)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
Reference land pattern layout (reference IPC7351 SOP65P640X120-29CM);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
PCB Layout Reference View
Exposed thermal pad (bottom surface)
4.40 ±0.10 6.40 ±0.20
(1.00)
9.70 ±0.10
C
C
0.60 ±0.15
4° ±4
0.15
+0.05
–0.06
0.25
+0.05
–0.06
Automotive Full Bridge MOSFET Driver
A3921
21
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Copyright ©2011-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to
permit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, LLC assumes no re spon si bil i ty for its
use; nor for any in fringe ment of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

A3921KLPTR-T

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Buy A3921KLPTR-T
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Description:
IC FULL BRIDGE CTLR 28TSSOP
Lifecycle:
New from this manufacturer.
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