Automotive Full Bridge MOSFET Driver
A3921
17
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
P
CPUMP
or
[( 2 V
BB
) – V
REG
] I
AV
, for V
BB
< 15 V,
=
[V
BB
– V
REG
] I
AV
, for V
BB
≥ 15 V,
=
(9)
P
SWITCHING
Q
GATE
× V
REG
× N × f
PWM
× Ratio ;
=
(10)
where:
I
AV
Q
GATE
× N × f
PWM
,
=
N is the number of FETs switching during a PWM cycle, and
Ratio
R
GATE
+ 10
.
10
=
N = 1 for slow decay with diode recirculation, N = 2 for slow decay
with synchronous rectification or for fast decay with diode recir-
culation, and N = 4 for fast decay with synchronous rectification.
Layout Recommendations
Careful consideration must be given to PCB layout when design-
ing high frequency, fast switching, high current circuits. The
following are recommendations regarding some of these consid-
erations:
• The A3921 ground, GND, and the high-current return of the
external FETs should return separately to the negative side
of the motor supply filtering capacitor. This will minimize
the effect of switching noise on the device logic and analog
reference.
• The exposed thermal pad should be connected to the GND
pin and may form part of the Controller Supply ground (see
figure 4).
• Minimize stray inductance by using short, wide copper traces at
the drain and source terminals of all power FETs. This includes
motor lead connections, the input power bus, and the common
source of the low-side power FETs. This will minimize voltages
induced by fast switching of large load currents.
• Consider the use of small (100 nF) ceramic decoupling
capacitors across the sources and drains of the power FETs to
limit fast transient voltage spikes caused by the inductance of
the circuit trace.
• Keep the gate discharge return connections Sx and LSS as short
as possible. Any inductance on these traces will cause negative
transitions on the corresponding A3921 pins, which may exceed
the absolute maximum ratings. If this is likely, consider the use
of clamping diodes to limit the negative excursion on these pins
with respect to GND.
• Sensitive connections such as RDEAD and VDSTH, which
have very little ground current, should be connected to the Quiet
ground (refer to figure 4), which is connected independently,
closest to the GND pin. These sensitive components should
never be connected directly to the supply common or to a
common ground plane. They must be referenced directly to the
GND pin.
• The supply decoupling for VBB, VREG, and V5 should
be connected to the Controller Supply ground, which is
independently connected close to the GND pin. The decoupling
capacitors should also be connected as close as practicable to
the relevant supply pin.
• If layout space is limited, then the Quiet and Controller Supply
grounds may be combined. In this case, ensure that the ground
return of the dead time resistor is close to the GND pin.
• Check the peak voltage excursion of the transients on the LSS
pin with reference to the GND pin, using a close grounded (tip
and barrel) probe. If the voltage at LSS exceeds the absolute
maximum shown in this datasheet, add either or both of
additional clamping and capacitance between the LSS pin and
the GND pin, as shown in figure 4.
• Gate charge drive paths and gate discharge return paths may
carry a large transient current pulse. Therefore, the traces from
GHx, GLx, Sx, and LSS should be as short as possible to reduce
the circuit trace inductance.
• Provide an independent connection from LSS to the common
point of the power bridge. It is not recommended to connect
LSS directly to the GND pin, as this may inject noise into
sensitive functions such as the timer for dead time.
• A low-cost diode can be placed in the connection to VBB to
provide reverse battery protection. In reverse battery conditions,
it is possible to use the body diodes of the power FETs to clamp
the reverse voltage to approximately 4 V. In this case, the
additional diode in the VBB connection will prevent damage
to the A3921 and the VDRAIN input will survive the
reverse voltage.
Note that the above are only recommendations. Each application
is different and may encounter different sensitivities. A driver
running a few amps will be less susceptible than one running with
150 A, and each design should be tested at the maximum current
to ensure any parasitic effects are eliminated.
