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5P49V5914B000NLGI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P37
PROGRAMMABLE CLOCK GENERATOR 16 MARCH 3, 2017
5P49V5914 DATASHEET
Table 17:DC Electrical Characteristics for LVDS(V
DDO
= 3.3V+5% or 2.5V+5%, TA = -40°C to +85°C)
Table 18:DC Electrical Characteristics for LVDS (V
DDO
= 1.8V+5%, TA = -40°C to +85°C)
Table 19:DC Electrical Characteristics for LVPECL (V
DDO
= 3.3V+5% or 2.5V+5%, TA = -40°C to
+85°C)
Symbol Parameter Min Typ Max Unit
V
OT
(+)
Differential Output Voltage for the TRUE binary state
247 454 mV
V
OT
(-)
Differential Output Voltage for the FALSE binary state
-247 -454 mV
V
OT
Change in V
OT
between Complimentary Output States
50 mV
V
OS
Output Common Mode Voltage (Offset Voltage)
1.125 1.25 1.375 V
V
OS
Change in V
OS
between Complimentary Output States
50 mV
I
OS
Outputs Short Circuit Current, V
OUT
+ or V
OUT
- = 0V or V
DDO
924mA
I
OSD
Differential Outputs Short Circuit Current, V
OUT
+ = V
OUT
-
612mA
Symbol Parameter Min Typ Max Unit
V
OT
(+)
Differential Output Voltage for the TRUE binary state
247 454 mV
V
OT
(-)
Differential Output Voltage for the FALSE binary state
-247 -454 mV
V
OT
Change in V
OT
between Complimentary Output States
50 mV
V
OS
Output Common Mode Voltage (Offset Voltage)
0.8 0.875 0.95 V
V
OS
Change in V
OS
between Complimentary Output States
50 mV
I
OS
Outputs Short Circuit Current, V
OUT
+ or V
OUT
- = 0V or V
DDO
924mA
I
OSD
Differential Outputs Short Circuit Current, V
OUT
+ = V
OUT
-
612mA
Symbol Parameter Min Typ Max Unit
V
OH
Output Voltage HIGH, terminated through 50 tied to V
DD
- 2 V
V
DDO
- 1.19 V
DDO
- 0.69 V
V
OL
Output Voltage LOW, terminated through 50 tied to V
DD
- 2 V
V
DDO
- 1.94 V
DDO
- 1.4 V
V
SWING
Peak-to-Peak Output Voltage Swing
0.55 0.993 V
MARCH 3, 2017 17 PROGRAMMABLE CLOCK GENERATOR
5P49V5914 DATASHEET
Table 20:Electrical Characteristics – DIF 0.7V HCSL Differential Outputs (V
DDO
= 3.3V±5%,
2.5V±5%, TA = -40°C to +85°C)
Symbol Parameter Conditions Min Typ Max Units Notes
dV/dt Slew Rate Scope averaging on 1 4 V/ns 1,2,3
Δ
dV/dt
Slew Rate Scope averaging on 20 % 1,2,3
VHIGH Voltage High 660 850 mV 1,6,7
VLOW Voltage Low -150 150 mV 1,6
VMAX Maximum Voltage 1150 mV 1
VMIN Minimum Voltage -300 mV 1
VSWING Voltage Swing
Scope averaging off
300 mV 1,2,6
VCROSS Crossing Voltage Value
Scope averaging off
250 550 mV 1,4,6
?VCROSS Crossing Voltage variation
Scope averaging off
140 mV 1,5
Note 7. Measured with scope averaging off, using statistics function. Variation is difference between min. and max.
Note 4: VCROSS is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge (i.e.
Clock rising and Clock# falling).
Note 5: the total variation of all VCROSS measurements in any particular system. Note that this is a subset of VCROSS min/max (VCROSS absolute)
allowed. The intent is to limit VCROSS induced modulation by setting ?VCROSS to be smaller than VCROSS absolute.
Note 6: Measured from single-ended waveform.
Statistical measurement on single-ended
signal using oscilloscope math function
(Scope averaging ON)
Measurement on single-ended signal using
absolute value (Scope averaging off)
Note 1: Guaranteed by design and characterization. Not 100% tested in production
Note 2: Measured from differential waveform.
Note 3: Slew rate is measured through the VSWING voltage range centered around differential 0V. This results in a +/-150mV window around differntial
0V.
PROGRAMMABLE CLOCK GENERATOR 18 MARCH 3, 2017
5P49V5914 DATASHEET
Table 21:1AC Timing Electrical Characteristics
(V
DDO
= 3.3V+5% or 2.5V+5% or 1.8V ±5%, TA = -40°C to +85°C)
(Spread Spectrum Generation = OFF)
Symbol
Parameter Test Conditions
Min. Typ. Max. Units
Input frequency limit (XIN)
840MHz
Input frequency limit (REF)
1200MHz
Input frequency limit (CLKIN, CLKINB)
1350MHz
Single ended clock output limit (LVCMOS)
1200
Differential clock output limit (LVPECL/
LVDS/HCSL)
1350
fVCO VCO Frequency
VCO operating frequency range
2500 2900 MHz
fPFD PFD Frequency
PFD operating frequency range 1
1
150 MHz
fBW Loop Bandwidth Input frequency = 25MHz 0.06 0.9 MHz
t2 Input Duty Cycle
Duty Cycle
45 55 %
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX= 2.5V or
3.3V
45 50 55 %
Measured at VDD/2, all outputs except
Reference output OUT0, VDDOX=1.8V
40 50 60 %
Measured at VDD/2, Reference output
OUT0 (5MHz - 120MHz) with 50% duty
cycle input
40 50 60 %
Measured at VDD/2, Reference output
OUT0 (150.1MHz - 200MHz) with 50% duty
cycle input
30 50 70 %
Slew Rate, SLEW[1:0] = 00
1.0
2.2
Slew Rate, SLEW[1:0] = 01
1.2
2.3
Slew Rate, SLEW[1:0] = 10
1.3
2.4
Slew Rate, SLEW[1:0] = 11
1.7
2.7
Slew Rate, SLEW[1:0] = 00
0.6
1.3
Slew Rate, SLEW[1:0] = 01
0.7
1.4
Slew Rate, SLEW[1:0] = 10
0.6
1.4
Slew Rate, SLEW[1:0] = 11
1.0
1.7
Slew Rate, SLEW[1:0] = 00
0.3
0.7
Slew Rate, SLEW[1:0] = 01
0.4
0.8
Slew Rate, SLEW[1:0] = 10
0.4
0.9
Slew Rate, SLEW[1:0] = 11
0.7
1.2
Rise Times
LVDS, 20% to 80%
300
Fall Times
LVDS, 80% to 20%
300
Rise Times
LVPECL, 20% to 80%
400
Fall Times
LVPECL, 80% to 20%
400
Single-ended 2.5V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=2.5V
Single-ended 1.8V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=1.8V
fOUT Output Frequency MHz
t4
2
Single-ended 3.3V LVCMOS output clock
rise and fall time, 20% to 80% of VDDO
(Output Load = 5 pF) VDDOX=3.3V
V/ns
fIN
1
Input Frequency
t3
5
Output Duty Cycle
t5 ps
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5P49V5914B000NLGI

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Manufacturer:
IDT
Description:
Clock Generators & Support Products VersaClock 5 CLK Gen PLL 3 Config Pairs
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