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P89LPC9331FDH,512

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90P91-P93P94-P94
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P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5.1 — 20 August 2012 28 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
[1] All ports are in input only (high-impedance) state after power-up.
[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3] The RSTSRC register reflects the cause of the P89LPC9351/9361 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the
power-on reset value is x011 0000.
[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.
TPCR2L Prescaler control
register low
CAH TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0 00 0000 0000
TRIM Internal oscillator
trim register
96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
[5][6]
WDCON Watchdog control
register
A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK
[4][6]
WDL Watchdog load C1H FF 1111 1111
WFEED1 Watchdog feed 1 C2H
WFEED2 Watchdog feed 2 C3H
Table 6. Special function registers - P89LPC9351/9361
* indicates SFRs that are bit addressable.
Name Description SFR
addr.
Bit functions and addresses Reset value
MSB LSB Hex Binary
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xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5.1 — 20 August 2012 29 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are
used to access these extended SFRs.
[2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset.
[3] CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit
comes from UCFG2.7.
[4] On power-on reset and watchdog reset, the PGAxTRIM8X16X and PGAxTRIM2X4X registers are initialized with a factory preprogrammed value. Other resets will not cause
initialization.
Table 7. Extended special function registers - P89LPC9351/9361
[1]
Name Description SFR
addr.
Bit functions and addresses Reset value
MSB LSB Hex Binary
BODCFG BOD
configuration
register
FFC8H------BOICFG1BOICFG0
[2]
CLKCON CLOCK
Control
register
FFDEH CLKOK - - XTALWD CLKDBL FOSC2 FOSC1 FOSC0
[3]
1000 xxxx
PGACON1 PGA1 control
register
FFE1H ENPGA1 PGASEL1
1
PGASEL1
0
PGATRIM
1
- - PGAG11 PGAG10 00 0000 0000
PGACON1B PGA1 control
register B
FFE4H - - - - - - - PGAENO
FF1
00 0000 0000
PGA1TRIM8X16X PGA1 trim
register
FFE3H 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIM0 8XTRIM3 8XTRIM2 8XTRIM1 8XTRIM0
[4]
PGA1TRIM2X4X PGA1 trim
register
FFE2H 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIM0 2XTRIM3 2XTRIM2 2XTRIM1 2XTRIM0
[4]
PGACON0 PGA0 control
register
FFCAH ENPGA0 PGASEL0
1
PGASEL0
0
PGATRIM
0
TSEL1 TSEL0 PGAG01 PGAG00 00 0000 0000
PGACON0B PGA0 control
register B
FFCEH - - - - - - - PGAENO
FF0
00 0000 0000
PGA0TRIM8X16X PGA0 trim
register
FFCDH 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIM0 8XTRIM3 8XTRIM2 8XTRIM1 8XTRIM0
[4]
PGA0TRIM2X4X PGA0 trim
register
FFCCH 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIM0 2XTRIM3 2XTRIM2 2XTRIM1 2XTRIM0
[4]
RTCDATH Real-time
clock data
register high
FFBFH 00 0000 0000
RTCDATL Real-time
clock data
register low
FFBEH 00 0000 0000
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5.1 — 20 August 2012 30 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.2 Enhanced CPU
The P89LPC9331/9341/9351/9361 uses an enhanced 80C51 CPU which runs at
six times the speed of standard 80C51 devices. A machine cycle consists of two CPU
clock cycles, and most instructions execute in one or two machine cycles.
7.3 Clocks
7.3.1 Clock definitions
The P89LPC9331/9341/9351/9361 device has several internal clocks as defined below:
OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock
sources (see Figure 7
) and can also be optionally divided to a slower frequency (see
Section 7.11 “
CCLK modification: DIVM register”).
Remark: f
osc
is defined as the OSCCLK frequency.
CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine
cycle, and most instructions are executed in one to two machine cycles (two or four CCLK
cycles).
RCCLK — The internal 7.373 MHz RC oscillator output. The clock doubler option, when
enabled, provides an output frequency of 14.746 MHz.
PCLK — Clock for the various peripheral devices and is
CCLK
⁄
2
.
7.3.2 CPU clock (OSCCLK)
The P89LPC9331/9341/9351/9361 provides several user-selectable oscillator options in
generating the CPU clock. This allows optimization for a range of needs from high
precision to lowest possible cost. These options are configured when the flash is
programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an
oscillator using an external crystal, or an external clock source.
7.4 Crystal oscillator option
The crystal oscillator option can be optimized for low, medium, or high frequency crystals
covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK, and
RTC. Low speed oscillator option can be the clock source of WDT.
7.4.1 Low speed oscillator option
This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic
resonators are also supported in this configuration.
7.4.2 Medium speed oscillator option
This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic
resonators are also supported in this configuration.
7.4.3 High speed oscillator option
This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic
resonators are also supported in this configuration.
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P89LPC9331FDH,512

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Buy P89LPC9331FDH,512
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU IC 80C51 MCU FLASH 4K
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