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P89LPC9331FDH,512

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90P91-P93P94-P94
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5.1 — 20 August 2012 76 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
11. Dynamic characteristics
Table 14. Dynamic characteristics (12 MHz)
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
40
Cto+85
C for industrial applications,
40
Cto+125
C extended, unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
=12MHz Unit
Min Max Min Max
f
osc(RC)
internal RC oscillator
frequency
nominal f = 7.3728 MHz
trimmed to 1% at
T
amb
=25 C; clock
doubler option = OFF
(default)
7.189 7.557 7.189 7.557 MHz
nominal f = 14.7456 MHz;
clock doubler option = ON,
V
DD
= 2.7 V to 3.6 V
14.378 15.114 14.378 15.114 MHz
f
osc(WD)
internal watchdog
oscillator frequency
T
amb
=25 C 380 420 380 420 kHz
f
osc
oscillator frequency 0 12 - - MHz
T
cy(clk)
clock cycle time see Figure 41 83 - - - ns
f
CLKLP
low-power select clock
frequency
08--MHz
Glitch filter
t
gr
glitch rejection time P1.5/RST pin - 50 - 50 ns
any pin except P1.5/RST
- 15 - 15 ns
t
sa
signal acceptance time P1.5/RST pin 125 - 125 - ns
any pin except P1.5/RST
50 - 50 - ns
External clock
t
CHCX
clock HIGH time see Figure 41 33 T
cy(clk)
t
CLCX
33 - ns
t
CLCX
clock LOW time see Figure 41 33 T
cy(clk)
t
CHCX
33 - ns
t
CLCH
clock rise time see Figure 41 -8-8ns
t
CHCL
clock fall time see Figure 41 -8-8ns
Shift register (UART mode 0)
T
XLXL
serial port clock cycle
time
see Figure 42 16T
cy(clk)
- 1333 - ns
t
QVXH
output data set-up to
clock rising edge time
see Figure 42 13T
cy(clk)
- 1083 - ns
t
XHQX
output data hold after
clock rising edge time
see Figure 42 -T
cy(clk)
+ 20 - 103 ns
t
XHDX
input data hold after
clock rising edge time
see Figure 42 -0-0ns
t
XHDV
input data valid to clock
rising edge time
see Figure 42 150 - 150 - ns
SPI interface
f
SPI
SPI operating frequency
slave 0
CCLK
⁄
6
02.0MHz
master -
CCLK
⁄
4
-3.0MHz
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5.1 — 20 August 2012 77 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
T
SPICYC
SPI cycle time see Figure 43, 44, 45, 46
slave
6
⁄
CCLK
-500-ns
master
4
⁄
CCLK
-333-ns
t
SPILEAD
SPI enable lead time see Figure 45, 46
slave 250 - 250 - ns
t
SPILAG
SPI enable lag time see Figure 45, 46
slave 250 - 250 - ns
t
SPICLKH
SPICLK HIGH time see Figure 43, 44, 45, 46
master
2
⁄
CCLK
-165-ns
slave
3
⁄
CCLK
-250-ns
t
SPICLKL
SPICLK LOW time see Figure 43, 44, 45, 46
master
2
⁄
CCLK
-165-ns
slave
3
⁄
CCLK
-250-ns
t
SPIDSU
SPI data set-up time see Figure 43, 44, 45, 46
master or slave 100 - 100 - ns
t
SPIDH
SPI data hold time see Figure 43, 44, 45, 46
master or slave 100 - 100 - ns
t
SPIA
SPI access time see Figure 45, 46
slave 0 120 0 120 ns
t
SPIDIS
SPI disable time see Figure 45, 46
slave 0 240 - 240 ns
t
SPIDV
SPI enable to output
data valid time
see Figure 43, 44, 45, 46
slave - 240 - 240 ns
master - 167 - 167 ns
t
SPIOH
SPI output data hold
time
see Figure 43, 44, 45, 46 0-0-ns
t
SPIR
SPI rise time see Figure 43, 44, 45, 46
SPI outputs (SPICLK,
MOSI, MISO)
- 100 - 100 ns
SPI inputs (SPICLK,
MOSI, MISO, SS
)
- 2000 - 2000 ns
t
SPIF
SPI fall time see Figure 43, 44, 45, 46
SPI outputs (SPICLK,
MOSI, MISO)
- 100 - 100 ns
SPI inputs (SPICLK,
MOSI, MISO, SS
)
- 2000 - 2000 ns
Table 14. Dynamic characteristics (12 MHz)
…continued
V
DD
= 2.4 V to 3.6 V unless otherwise specified.
T
amb
=
40
Cto+85
C for industrial applications,
40
Cto+125
C extended, unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
=12MHz Unit
Min Max Min Max
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5.1 — 20 August 2012 78 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
Table 15. Dynamic characteristics (18 MHz)
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
40
Cto+85
C for industrial applications,
40
Cto+125
C extended, unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
=18MHz Unit
Min Max Min Max
f
osc(RC)
internal RC oscillator
frequency
nominal f = 7.3728 MHz
trimmed to 1% at
T
amb
=25 C; clock
doubler option = OFF
(default)
7.189 7.557 7.189 7.557 MHz
nominal f = 14.7456 MHz;
clock doubler option = ON
14.378 15.114 14.378 15.114 MHz
f
osc(WD)
internal watchdog
oscillator frequency
T
amb
=25 C 380 420 380 420 kHz
f
osc
oscillator frequency 0 18 - - MHz
T
cy(clk)
clock cycle time see Figure 41 55 - - - ns
f
CLKLP
low-power select clock
frequency
08--MHz
Glitch filter
t
gr
glitch rejection time P1.5/RST pin - 50 - 50 ns
any pin except P1.5/RST
- 15 - 15 ns
t
sa
signal acceptance time P1.5/RST pin 125 - 125 - ns
any pin except P1.5/RST
50 - 50 - ns
External clock
t
CHCX
clock HIGH time see Figure 41 22 T
cy(clk)
t
CLCX
22 - ns
t
CLCX
clock LOW time see Figure 41 22 T
cy(clk)
t
CHCX
22 - ns
t
CLCH
clock rise time see Figure 41 -5-5ns
t
CHCL
clock fall time see Figure 41 -5-5ns
Shift register (UART mode 0)
T
XLXL
serial port clock cycle
time
see Figure 42 16T
cy(clk)
- 888 - ns
t
QVXH
output data set-up to
clock rising edge time
see Figure 42 13T
cy(clk)
- 722 - ns
t
XHQX
output data hold after
clock rising edge time
see Figure 42 -T
cy(clk)
+ 20 - 75 ns
t
XHDX
input data hold after
clock rising edge time
see Figure 42 -0-0ns
t
XHDV
input data valid to clock
rising edge time
see Figure 42 150 - 150 - ns
SPI interface
f
SPI
SPI operating frequency
slave 0
CCLK
⁄
6
03.0MHz
master -
CCLK
⁄
4
-4.5MHz
T
SPICYC
SPI cycle time see Figure 43, 44, 45, 46
slave
6
⁄
CCLK
- 333 - ns
master
4
⁄
CCLK
- 222 - ns
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60P61-P63P64-P66P67-P69P70-P72P73-P75P76-P78P79-P81P82-P84P85-P87P88-P90P91-P93P94-P94

P89LPC9331FDH,512

Mfr. #:
Buy P89LPC9331FDH,512
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU IC 80C51 MCU FLASH 4K
Lifecycle:
New from this manufacturer.
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