P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5.1 — 20 August 2012 79 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Parts are tested to 2 MHz, but are guaranteed to operate down to 0 Hz.
t
SPILEAD
SPI enable lead time see Figure 45, 46
slave 250 - 250 - ns
t
SPILAG
SPI enable lag time see Figure 45, 46
slave 250 - 250 - ns
t
SPICLKH
SPICLK HIGH time see Figure 43, 44, 45, 46
slave
3
CCLK
- 167 - ns
master
2
CCLK
-111-ns
t
SPICLKL
SPICLK LOW time see Figure 43, 44, 45, 46
slave
3
CCLK
- 167 - ns
master
2
CCLK
-111-ns
t
SPIDSU
SPI data set-up time see Figure 43, 44, 45, 46
master or slave 100 - 100 - ns
t
SPIDH
SPI data hold time see Figure 43, 44, 45, 46
master or slave 100 - 100 - ns
t
SPIA
SPI access time see Figure 45, 46
slave 0 80 0 80 ns
t
SPIDIS
SPI disable time see Figure 45, 46
slave 0 160 - 160 ns
t
SPIDV
SPI enable to output
data valid time
see Figure 43, 44, 45, 46
slave - 160 - 160 ns
master - 111 - 111 ns
t
SPIOH
SPI output data hold
time
see Figure 43, 44, 45, 46 0-0-ns
t
SPIR
SPI rise time see Figure 43, 44, 45, 46
SPI outputs (SPICLK,
MOSI, MISO)
- 100 - 100 ns
SPI inputs (SPICLK,
MOSI, MISO, SS
)
- 2000 - 2000 ns
t
SPIF
SPI fall time see Figure 43, 44, 45, 46
SPI outputs (SPICLK,
MOSI, MISO)
- 100 - 100 ns
SPI inputs (SPICLK,
MOSI, MISO, SS
)
- 2000 - 2000 ns
Table 15. Dynamic characteristics (18 MHz) …continued
V
DD
= 3.0 V to 3.6 V unless otherwise specified.
T
amb
=
40
Cto+85
C for industrial applications,
40
Cto+125
C extended, unless otherwise specified.
[1][2]
Symbol Parameter Conditions Variable clock f
osc
=18MHz Unit
Min Max Min Max
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5.1 — 20 August 2012 80 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
11.1 Waveforms
Fig 41. External clock timing (with an amplitude of at least V
i(RMS)
= 200 mV)
t
CHCL
t
CLCX
t
CHCX
T
cy(clk)
t
CLCH
002aaa907
Fig 42. Shift register mode timing
01234567
valid valid valid valid valid valid valid valid
T
XLXL
002aaa906
set TI
set RI
t
XHQX
t
QVXH
t
XHDV
t
XHDX
clock
output data
write to SBUF
input data
clear RI
Fig 43. SPI master timing (CPHA = 0)
T
SPICYC
t
SPICLKH
t
SPICLKH
t
SPICLKL
t
SPICLKL
master LSB/MSB outmaster MSB/LSB out
t
SPIDH
t
SPIDSU
t
SPIF
t
SPIOH
t
SPIDV
t
SPIR
t
SPIDV
t
SPIF
t
SPIR
t
SPIF
t
SPIR
SS
SPICLK
(CPOL = 0)
(output)
002aaa908
SPICLK
(CPOL = 1)
(output)
MISO
(input)
MOSI
(output)
LSB/MSB in
MSB/LSB in
P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5.1 — 20 August 2012 81 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
Fig 44. SPI master timing (CPHA = 1)
T
SPICYC
t
SPICLKL
t
SPICLKL
t
SPICLKH
t
SPICLKH
master LSB/MSB outmaster MSB/LSB out
t
SPIDH
t
SPIDSU
t
SPIF
t
SPIOH
t
SPIDV
t
SPIR
t
SPIDV
t
SPIF
t
SPIF
t
SPIR
t
SPIR
SS
SPICLK
(CPOL = 0)
(output)
002aaa909
SPICLK
(CPOL = 1)
(output)
MISO
(input)
MOSI
(output)
LSB/MSB in
MSB/LSB in
Fig 45. SPI slave timing (CPHA = 0)
T
SPICYC
t
SPICLKH
t
SPICLKH
t
SPICLKL
t
SPICLKL
t
SPILEAD
t
SPILAG
t
SPIDSU
t
SPIDH
t
SPIDH
t
SPIDSU
t
SPIDSU
t
SPIF
t
SPIA
t
SPIOH
t
SPIDIS
t
SPIR
slave MSB/LSB out
MSB/LSB in LSB/MSB in
slave LSB/MSB out
t
SPIDV
t
SPIOH
t
SPIOH
t
SPIDV
t
SPIR
t
SPIR
t
SPIF
t
SPIF
SS
SPICLK
(CPOL = 0)
(input)
002aaa910
SPICLK
(CPOL = 1)
(input)
MISO
(output)
MOSI
(input)
not defined

P89LPC9331FDH,512

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Microcontrollers - MCU 8-bit Microcontrollers - MCU IC 80C51 MCU FLASH 4K
Lifecycle:
New from this manufacturer.
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