P89LPC9331_9341_9351_9361 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5.1 — 20 August 2012 58 of 94
NXP Semiconductors
P89LPC9331/9341/9351/9361
8-bit microcontroller with accelerated two-clock 80C51 core
7.30.10 Hardware activation of the bootloader
The bootloader can also be executed by forcing the device into ISP mode during a
power-on sequence (see the P89LPC9331/9341/9351/9361 User manual for specific
information). This has the same effect as having a non-zero status byte. This allows an
application to be built that will normally execute user code but can be manually forced into
ISP operation. If the factory default setting for the boot is changed, it will no longer point to
the factory pre-programmed ISP bootloader code. After programming the flash, the status
byte should be programmed to zero in order to allow execution of the user’s application
code beginning at address 0000H.
7.31 User configuration bytes
Some user-configurable features of the P89LPC9331/9341/9351/9361 must be defined at
power-up and therefore cannot be set by the program after start of execution. These
features are configured through the use of the flash byte UCFG1 and UCFG2. Please see
the P89LPC9331/9341/9351/9361 User manual for additional details.
7.32 User sector security bytes
There are 4/8/6 User Sector Security Bytes on the P89LPC9331/9341/9351/9361. Each
byte corresponds to one sector. Please see the P89LPC9331/9341/9351/9361 User
manual for additional details.
8. ADC
8.1 General description
The P89LPC9331/9341/9351/9361 has two 8-bit, 4-channel multiplexed successive
approximation analog-to-digital converter modules. An on-chip temperature sensor is
integrated within ADC0 and operates over wide temperature. In P89LPC9351/9361, two
high-speed programmable gain amplifiers (PGA) are integrated. The PGAs provide
selectable gains of 2x, 4x, 8x, or 16x. A block diagram of the ADC is shown in Figure 23
and Figure 24
.
Each ADC consists of a 4-input multiplexer which feeds a sample-and-hold circuit
providing an input signal to comparator inputs. The control logic in combination with the
SAR drives a digital-to-analog converter which provides the other input to the comparator.
The output of the comparator is fed to the SAR.
8.2 Features and benefits
Two 8-bit, 4-channel multiplexed input, successive approximation ADCs.
P89LPC9341 1FH 1F00H 1E00H to 1FFFH 1C00H to 1FFFH
P89LPC9351 1FH 1F00H 1E00H to 1FFFH 1C00H to 1FFFH
P89LPC9361 3FH 3F00H 3E00H to 3FFFH 3C00H to 3FFFH
Table 10. Default boot vector values and ISP entry points
…continued
Device Default
boot vector
Default
bootloader
entry point
Default bootloader
code range
1 kB sector
range
