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AR0130CSSM00SPCAH-S115-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
AR0130CS
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19
Figure 17. Frame Format with Embedded Data Lines Enabled
Image
Register Data
Status & Statistics Data
HBlank
VBlank
Embedded Data
The embedded data contains the configuration of the
image being displayed. This includes all register settings
used to capture the current frame. The registers embedded
in these rows are as follows:
Line 1:
Registers R0x3000 to R0x312F
Line 2:
Registers R0x3136 to R0x31BF, R0x31D0 to R0x31FF
NOTE: All undefined registers will have a value of 0.
In parallel mode, since the pixel word depth is
12−bits/pixel, the sensor 16−bit register data will be
transferred over 2 pixels where the register data will be
broken up into 8 MSB and 8 LSB. The alignment of the 8−bit
data will be on the 8 MSB bits of the 12−bit pixel word. For
example, of a register value of 0x1234 is to be transmitted,
it will be transmitted over 2, 12−bit pixels as follows: 0x120,
0x340.
The first pixel of each line in the embedded data is a tag
value of 0x0A0. This signifies that all subsequent data is 8
bit data aligned to the MSB of the 12−bit pixel.
The figure below summarizes how the embedded data
transmission looks like. It should be noted that data, as
shown in Figure 18, is aligned to the MSB of each word:
Figure 18. Format of Embedded Data Output within a Frame
{register_
value_LSB}
8’h5A
Data line 1
Data line 2
8’h5A
8’hAA
{register_
address_MSB}
8’hA5
{register_
address_LSB}
8’h5A
{register_
value_MSB}
8’h5A
{register_
value_LSB}
data_format_
code =8’h0A
8’hAA
{register_
address_MSB}
8’hA5
{register_
address_LSB}
8’h5A
{register_
value_MSB}
8’h5A
data_format_
code =8’h0A
The data embedded in these rows are as follows:
• 0x0A0 − identifier
• 0xAA0
• Register Address MSB of the first register
• 0xA50
• Register Address LSB of the first register
• 0x5A0
• Register Value MSB of the first register addressed
• 0x5A0
• Register Value LSB of the first register addressed
• 0x5A0
• Register Value MSB of the register at first address + 2
• 0x5A0
• Register Value LSB of the register at first address + 2
• 0x5A0
• etc.
AR0130CS
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20
Embedded Statistics
The embedded statistics contain frame identifiers and
histogram information of the image in the frame. This can be
used by downstream auto−exposure algorithm blocks to
make decisions about exposure adjustment.
This histogram is divided into 244 bins with a bin spacing
of 64 evenly spaced bins for digital code values 0 to 2
12
, 120
evenly spaced bins for values 2
12
to 2
16
, 60 evenly spaced
bins for values 2
16
to 2
20
.
The first pixel of each line in the embedded statistics is a
tag value of 0x0B0. This signifies that all subsequent
statistics data is 10 bit data aligned to the MSB of the 12−bit
pixel.
The figure below summarizes how the embedded
statistics transmission looks like. It should be noted that
data, as shown in Figure 19, is aligned to the msb of each
word:
Figure 19. Format of Embedded Statistics Output within a Frame
lowEndMean
[19:10]
stats line 1
stats line 2
histogram
bin1 [9:0]
#words =
10’h1EC
{2’b00, frame
_count MSB}
{2’b00, frame
_ID MSB}
{2’b00, frame
_ID LSB}
histogram
bin0 [19:10]
histogram
bin0 [9:0]
histogram
bin1 [19:10]
data_format_
code =8’h0B
#words =
10’h1C
mean [ 19:10]
mean [9:0]
hist_begin
[19:10]
hist_begin
[9:10]
8’h07
data_format_
code =8’h0B
{2’b00, frame
_count LSB}
8’h07
histogram
bin243 [19:10]
histogram
bin243 [9:0]
8’h07
hist_end
[19:10]
hist_end
[9:10]
lowEndMean
[9:0]
perc_lowEnd
[19:10]
perc_lowEnd
[9:0]
norm_abs_dev
[19:10]
lnorm_abs_dev
[9:0]
The statistics embedded in these rows are as follows:
Line 1:
• 0x0B0 − identifier
• Register 0x303A − frame_count
• Register 0x31D2 − frame ID
• Histogram data − histogram bins 0−243
Line 2:
• 0x0B0 (identifier)
• Mean
• Histogram Begin
• Histogram End
• Low End Histogram Mean
• Percentage of Pixels Below Low End Mean
• Normal Absolute Deviation
Gain
Digital Gain
Digital gain can be controlled globally by R0x305E
(Context A) or R0x30C4 (Context B). There are also
registers that allow individual control over each Bayer color
(GreenR, GreenB, Red, Blue).
The format for digital gain setting is xxx.yyyyy where
0b00100000 represents a 1x gain setting and 0b00110000
represents a 1.5x gain setting. The step size for yyyyy is
0.03125 while the step size for xxx is 1. Therefore to set a
gain of 2.09375 one would set digital gain to 01000011.
Analog Gain
The AR0130 has a column parallel architecture and
therefore has an Analog gain stage per column.
There are two stages of analog gain, the first stage can be
set to 1x, 2x, 4x or 8x. This is can be set in
R0x30B0[5:4](Context A) or R0x30B0[9:8] (Context B).
The second stage is capable of setting an additional 1x or
1.25x gain which can be set in R0x3EE4[8].
This allows the maximum possible analog gain to be set
to 10x.
Black Level Correction
Black level correction is handled automatically by the
image sensor. No adjustments are provided except to enable
or disable this feature. Setting R0x30EA[15] disables the
automatic black level correction. Default setting is for
automatic black level calibration to be enabled.
The automatic black level correction measures the
average value of pixels from a set of optically black lines in
the image sensor. The pixels are averaged as if they were
light−sensitive and passed through the appropriate gain.
This line average is then digitally low−pass filtered over
many frames to remove temporal noise and random
instabilities associated with this measurement. The new
filtered average is then compared to a minimum acceptable
level, low threshold, and a maximum acceptable level, high
threshold. If the average is lower than the minimum
acceptable level, the offset correction value is increased by
a predetermined amount. If it is above the maximum level,
the offset correction value is decreased by a predetermined
amount. The high and low thresholds have been calculated
to avoid oscillation of the black level from below to above
the targeted black level. At high gain, long exposure, and
high temperature conditions, the performance of this
function can degrade.
AR0130CS
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21
Row−wise Noise Correction
Row (Line)−wise Noise Correction is handled
automatically by the image sensor. No adjustments are
provided except to enable or disable this feature. Clearing
R0x3044[10] disables the row noise correction. Default
setting is for row noise correction to be enabled.
Row−wise noise correction is performed by calculating an
average from a set of optically black pixels at the start of
each line and then applying each average to all the active
pixels of the line.
Column Correction
The AR0130 uses column parallel readout architecture to
achieve fast frame rate. Without any corrections, the
consequence of this architecture is that different column
signal paths have slightly different offsets that might show
up on the final image as structured fixed pattern noise.
AR0130 has column correction circuitry that measures
this offset and removes it from the image before output. This
is done by sampling dark rows containing tied pixels and
measuring an offset coefficient per column to be corrected
later in the signal path.
Column correction can be enabled/disabled via
R0x30D4[15]. Additionally, the number of rows used for
this offset coefficient measurement is set in R0x30D4[3:0].
By default this register is set to 0x7, which means that 8 rows
are used. This is the recommended value. Other control
features regarding column correction can be viewed in the
AR0130 Register reference. Any changes to column
correction settings need to be done when the sensor
streaming is disabled and the appropriate triggering
sequence must be followed as described below.
Column Correction Triggering
Column correction requires a special procedure to trigger
depending on which state the sensor is in.
Column Triggering on Startup
When streaming the sensor for the first time after
power−up, a special sequence needs to be followed to make
sure that the column correction coefficients are internally
calculated properly.
1. Follow proper power up sequence for power
supplies and clocks
2. Apply sequencer settings if needed
3. Apply frame timing and PLL settings as required
by application
4. Set analog gain to 1x and low conversion gain
5. Enable column correction and settings
6. Disable auto re−trigger for change in conversion
gain or col_gain, and enable column correction
always. (R0x30BA = 0x0008).
7. Enable streaming (R0x301A[2] = 1) or drive the
TRIGGER pin HIGH.
8. Wait 9 frames to settle. (First frame after coming
up from standby is internally column correction
disabled.)
9. Disable streaming (R0x301A[2] = 0) or drive the
TRIGGER pin LOW.
After this, the sensor has calculated the proper column
correction coefficients and the sensor is ready for streaming.
Any other settings (including gain, integration time and
conversion gain etc.) can be done afterwards without
affecting column correction.
Column Correction Retriggering Due to Mode Change
Since column offsets is sensitive to changes in the analog
signal path, such changes require column correction
circuitry to be retriggered for the new path. Examples of
such mode changes include: horizontal mirror, vertical
mirror, changes to column correction settings.
When such changes take place, the following sequence
needs to take place:
1. Disable streaming (R0x301A[2]=0) or drive the
TRIGGER pin LOW.
2. Enable streaming (R0x301A[2]=1) or drive the
TRIGGER pin HIGH.
3. Wait 9 frames to settle.
NOTE: The above steps are not needed if the sensor is
being reset (soft or hard reset) upon the mode
change.
Test Patterns
The AR0130 has the capability of injecting a number of
test patterns into the top of the datapath to debug the digital
logic. With one of the test patterns activated, any of the
datapath functions can be enabled to exercise it in a
deterministic fashion. Test patterns are selected by
Test_Pattern_Mode register (R0x3070). Only one of the test
patterns can be enabled at a given point in time by setting the
Test_Pattern_Mode register according to Table 7. When test
patterns are enabled the active area will receive the value
specified by the selected test pattern and the dark pixels will
receive the value in Test_Pattern_Green (R0x3074 and
R0x3078) for green pixels, Test_Pattern_Blue (R0x3076)
for blue pixels, and Test_Pattern_Red (R0x3072) for red
pixels.
NOTE: Turn off black level calibration (BLC) when
Test Pattern is enabled.
Table 7. TEST PATTERN MODES
Test_Pattern_Mode Test Pattern Output
0 No test pattern (normal operation)
1 Solid color test pattern
2 100% color bar test pattern
3 Fade−to−gray color bar test pattern
256 Walking 1s test pattern (12−bit)
Color Field
When the color field mode is selected, the value for each
pixel is determined by its color. Green pixels will receive the
value in Test_Pattern_Green, red pixels will receive the
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AR0130CSSM00SPCAH-S115-GEVB

Mfr. #:
Buy AR0130CSSM00SPCAH-S115-GEVB
Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 1.2 MP 1/3 CIS HB
Lifecycle:
New from this manufacturer.
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