AR0130CS
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25
Sequential READ, Start from Current Location
This sequence (Figure 23) starts in the same way as the
single READ from current location (Figure 21). Instead of
generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge
bit and continues to perform byte READs until “L” bytes
have been read.
Figure 23. Sequential READ, Start from Current Location
N+LN+L−1N+2N+1Previous Reg Address, N
PAS 1 Read DataASlave Address Read DataRead Data Read DataAAA
Single WRITE to Random Location
This sequence (Figure 24) begins with the master
generating a start condition. The slave address/data
direction byte signals a WRITE and is followed by the HIGH
then LOW bytes of the register address that is to be written.
The master follows this with the byte of write data.
The WRITE is terminated by the master generating a stop
condition.
Figure 24. Single WRITE to Random Location
Previous Reg Address, N Reg Address, M M+1
S0 PSlave Address Reg Address[15:8] Reg Address[7:0]
A
A
A
A A Write Data
Sequential WRITE, Start at Random Location
This sequence (Figure 25) starts in the same way as the
single WRITE to random location (Figure 24). Instead of
generating a no-acknowledge bit after the first byte of data
has been transferred, the master generates an acknowledge
bit and continues to perform byte WRITEs until “L” bytes
have been written. The WRITE is terminated by the master
generating a stop condition.
Figure 25. Sequential WRITE, Start at Random Location
Previous Reg Address, N Reg Address, M M+1
S0Slave Address A Reg Address[15:8] A A AReg Address[7:0] Write Data
M+LM+L−1M+L−2M+1 M+2 M+3
Write Data AA
A
AP
A
Write Data Write Data Write Data
