AR0130CS
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23
TWO-WIRE SERIAL REGISTER INTERFACE
The two−wire serial interface bus enables read/write
access to control and status registers within the AR0130.
This interface is designed to be compatible with the
electrical characteristics and transfer protocols of the
two−wire serial interface specification.
The interface protocol uses a master/slave model in which
a master controls one or more slave devices. The sensor acts
as a slave device. The master generates a clock (S
CLK) that
is an input to the sensor and is used to synchronize transfers.
Data is transferred between the master and the slave on a
bidirectional signal (S
DATA). SDATA is pulled up to VDD_IO
off−chip by a 1.5 kW resistor. Either the slave or master
device can drive S
DATA LOW − the interface protocol
determines which device is allowed to drive S
DATA at any
given time.
The protocols described in the two−wire serial interface
specification allow the slave device to drive S
CLK LOW; the
AR0130 uses S
CLK as an input only and therefore never
drives it LOW.
Protocol
Data transfers on the two-wire serial interface bus are
performed by a sequence of low-level protocol elements:
1. a (repeated) start condition
2. a slave address/data direction byte
3. an (a no) acknowledge bit
4. a message byte
5. a stop condition
The bus is idle when both S
CLK
and S
DATA
are HIGH.
Control of the bus is initiated with a start condition, and the
bus is released with a stop condition. Only the master can
generate the start and stop conditions.
Start Condition
A start condition is defined as a HIGH-to-LOW transition
on S
DATA
while S
CLK
is HIGH. At the end of a transfer, the
master can generate a start condition without previously
generating a stop condition; this is known as a “repeated
start” or “restart” condition.
Stop Condition
A stop condition is defined as a LOW-to-HIGH transition
on S
DATA
while S
CLK
is HIGH.
Data Transfer
Data is transferred serially, 8 bits at a time, with the MSB
transmitted first. Each byte of data is followed by an
acknowledge bit or a no-acknowledge bit. This data transfer
mechanism is used for the slave address/data direction byte
and for message bytes.
One data bit is transferred during each S
CLK
clock period.
S
DATA
can change when S
CLK
is LOW and must be stable
while S
CLK
is HIGH.
Slave Address/Data Direction Byte
Bits [7:1] of this byte represent the device slave address
and bit [0] indicates the data transfer direction. A “0” in
bit [0] indicates a WRITE, and a “1” indicates a READ.
The default slave addresses used by the AR0130CS are 0x20
(write address) and 0x21 (read address) in accordance with
the specification. Alternate slave addresses of 0x30 (write
address) and 0x31 (read address) can be selected by enabling
and asserting the S
ADDR
input.
An alternate slave address can also be programmed
through R0x31FC.
Message Byte
Message bytes are used for sending register addresses and
register write data to the slave device and for retrieving
register read data.
Acknowledge Bit
Each 8-bit data transfer is followed by an acknowledge bit
or a no-acknowledge bit in the S
CLK
clock period following
the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases S
DATA
.
The receiver indicates an acknowledge bit by driving S
DATA
LOW. As for data transfers, S
DATA
can change when S
CLK
is LOW and must be stable while S
CLK
is HIGH.
No-Acknowledge Bit
The no-acknowledge bit is generated when the receiver
does not drive S
DATA
LOW during the S
CLK
clock period
following a data transfer. A no-acknowledge bit is used to
terminate a read sequence.
Typical Sequence
A typical READ or WRITE sequence begins by the
master generating a start condition on the bus. After the start
condition, the master sends the 8−bit slave address/data
direction byte. The last bit indicates whether the request is
for a read or a write, where a “0” indicates a write and a “1”
indicates a read. If the address matches the address of the
slave device, the slave device acknowledges receipt of the
address by generating an acknowledge bit on the bus.
If the request was a WRITE, the master then transfers the
16−bit register address to which the WRITE should take
place. This transfer takes place as two 8−bit sequences and
the slave sends an acknowledge bit after each sequence to
indicate that the byte has been received. The master then
transfers the data as an 8−bit sequence; the slave sends an
acknowledge bit at the end of the sequence. The master stops
writing by generating a (re)start or stop condition.
If the request was a READ, the master sends the 8−bit
write slave address/data direction byte and 16−bit register
address, the same way as with a WRITE request. The master
then generates a (re)start condition and the 8−bit read slave
address/data direction byte, and clocks out the register data,
eight bits at a time. The master generates an acknowledge bit
after each 8−bit transfer. The slave’s internal register address
is automatically incremented after every 8 bits are
transferred. The data transfer is stopped when the master
sends a no−acknowledge bit.
