AR0130CS
www.onsemi.com
34
POWER-ON RESET AND STANDBY TIMING
Power-Up Sequence
The recommended power-up sequence for the AR0130 is
shown in Figure 31. The available power supplies (V
DD
_IO,
V
DD
, V
DD
_SLVS, V
DD
_PLL, V
AA
, V
AA
_PIX) must have
the separation specified below.
1. Turn on V
DD
_PLL power supply.
2. After 010 ms, turn on V
AA
and V
AA
_PIX power
supply.
3. After 010 ms, turn on V
DD
power supply.
4. After 010 ms, turn on V
DD
_IO power supply.
5. After the last power supply is stable, enable
EXTCLK.
6. Assert RESET_BAR for at least 1 ms.
7. Wait 150,000 EXTCLKs (for internal initialization
into software standby).
8. Configure PLL, output, and image settings to
desired values.
9. Wait 1 ms for the PLL to lock.
10. Set streaming mode (R0x301a[2] = 1).
Figure 31. Power Up
EXTCLK
V
DD
_SLVS
V
AA
_PIX
V
AA
(2.8)
V
DD
_IO (1.8/2.8)
V
DD
(1.8)
V
DD
_PLL (2.8)
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
X
Hard
Reset
Internal Ini-
tialization
Software
Standby
PLL Clock Streaming
RESET_BAR
Table 19. POWER-UP SEQUENCE
Symbol Definition Min Typ Max Unit
t
0
V
DD
_PLL to V
AA
/V
AA
_PIX (Note 20) 0 10
ms
t
1
V
AA
/V
AA
_PIX to V
DD
0 10
ms
t
2
V
DD
to V
DD
_IO 0 (Note 21) 10
ms
t
3
V
DD
_IO to V
DD
_SLVS 0 10
ms
t
X
Xtal Settle Time 30 (Note 18) ms
t
4
Hard Reset 1 (Note 19) ms
t
5
Internal Initialization 150,000 EXTCLKs
t
6
PLL Lock Time 1 ms
18.Xtal settling time is component-dependent, usually taking about 10–100 ms.
19.Hard reset time is the minimum time required after power rails are settled. In a circuit where hard reset is held down by RC circuit, then the
RC time must include the all power rail settle time and Xtal settle time.
20.It is critical that V
DD
_PLL is not powered up after the other power supplies. It must be powered before or at least at the same time as the
others. If the case happens that V
DD
_PLL is powered after other supplies then the sensor may have functionality issues and will experience
high current draw on this supply.
21.For the case where V
DD
_IO is 2.8 V and V
DD
is 1.8 V, it is recommended that the minimum time be 5 ms.
AR0130CS
www.onsemi.com
35
Power-Down Sequence
The recommended power-down sequence for the AR0130
is shown in Figure 32. The available power supplies
(V
DD
_IO, V
DD
, V
DD
_SLVS, V
DD
_PLL, V
AA
, V
AA
_PIX)
must have the separation specified below.
1. Disable streaming if output is active by setting
standby R0x301a[2] = 0.
2. The soft standby state is reached after the current
row or frame, depending on configuration, has
ended.
3. Turn off V
DD
_SLVS, if used.
4. Turn off V
DD
_IO.
5. Turn off V
DD
.
6. Turn off V
AA
/V
AA
_PIX.
7. Turn off V
DD
_PLL.
Figure 32. Power Down
EXTCLK
V
DD
_PLL (2.8)
V
DD
_IO (1.8/2.8)
V
DD
(1.8)
V
DD
_SLVS
t
0
Power Down until Next
Power Up Cycle
t
1
t
2
t
3
t
4
V
AA
_PIX
V
AA
(2.8)
Table 20. POWER-DOWN SEQUENCE
Symbol
Parameter Min Typ Max Unit
t
0
V
DD
_SLVS to V
DD
_IO 0
ms
t
1
V
DD
_IO to V
DD
0
ms
t
2
V
DD
to V
AA
/V
AA
_PIX 0
ms
t
3
V
AA
/V
AA
_PIX to V
DD
_PLL 0
ms
t
4
PwrDn until Next PwrUp Time 100 ms
22.t
4
is required between power down and next power up time; all decoupling caps from regulators must be completely discharged.
PLCC48 11.43x11.43
CASE 776AL
ISSUE A
DATE 21 DEC 201
7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
http://onsemi.com
1
© Semiconductor Components Industries, LLC, 2002
October, 2002 − Rev. 0
Case Outline Number:
XXX
DOCUMENT NUMBER:
STATUS:
REFERENCE:
DESCRIPTION:
98AON93134F
ON SEMICONDUCTOR STANDARD
PLCC48 11.43X11.43
Electronic versions are uncontrolled except when
accessed directly from the Document Repository. Printed
versions are uncontrolled except when stamped
“CONTROLLED COPY” in red.
PAGE 1 OF 2

AR0130CSSM00SPCAH-S115-GEVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 1.2 MP 1/3 CIS HB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union