AR0130CS
www.onsemi.com
4
Figure 2. Typical Configuration: Parallel Pixel Data Interface
V
AA
_PIXV
AA
V
DD
_PLLV
DD
V
DD
_IO
From Controller
Master Clock
(6 − 50 MHz)
1.5 kW
2
1.5 kW
2,3
Digital
I/O
Power
1
Digital
Core
Power
1
PLL
Power
1
Analog
Power
1
S
DATA
S
ADDR
S
CLK
TRIGGER
OE_BAR
STANDBY
RESET_BAR
Reserved
D
OUT
[11:0]
PIXCLK
FRAME_VALID
LINE_VALID
Analog
Power
1
D
GND
A
GND
Digital
Ground
Analog
Ground
V
AA
V
AA
_PIXV
DD
_PLLV
DD
_IO V
DD
EXTCLK
To Controller
Notes:
1. All power supplies must be adequately decoupled.
2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.
3. This pull−up resistor is not required if the controller drives a valid logic level on S
CLK
at all times.
4. ON Semiconductor recommends that VDD_SLVS pad (only available in bare die) is left unconnected.
5. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as
close as possible to the pad. Actual values and results may vary depending on layout and design considerations.
Check the AR0130 demo headboard schematics for circuit recommendations.
6. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital
power planes is minimized.
7. I/O signals voltage must be configured to match V
DD
_IO voltage to minimize any leakage current.
Table 3. PAD DESCRIPTIONS
Name Type Description
STANDBY Input Standby−mode enable pin (active HIGH).
V
DD
_PLL Power PLL power.
V
AA
Power Analog power.
EXTCLK Input External input clock.
V
DD
_SLVS Power Digital power (do not connect).
D
GND
Power Digital ground.
V
DD
Power Digital power.
A
GND
Power Analog ground.
S
ADDR
Input Two−Wire Serial Interface address select.
S
CLK
Input Two−Wire Serial Interface clock input.
S
DATA
I/O Two−Wire Serial Interface data I/O.
