OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AR0130CSSM00SPCAH-S115-GEVB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40
AR0130CS
www.onsemi.com
28
Table 8. TWO-WIRE SERIAL BUS CHARACTERISTICS (continued)
(f
EXTCLK
= 27 MHz; V
DD
= 1.8 V; V
DD
_IO = 2.8 V; V
AA
= 2.8 V; V
AA
_PIX = 2.8 V; V
DD
_PLL = 2.8 V; T
A
= 25°C)
Parameter Unit
Fast-ModeStandard Mode
Symbol
Parameter Unit
MaxMinMaxMin
Symbol
Bus Free Time between a STOP
and START Condition
t
BUF
4.7 − 1.3 −
ms
Capacitive Load for each Bus Line Cb − 400 − 400 pF
Serial Interface Input Pin Capaci-
tance
CIN_SI − 3.3 − 3.3 pF
S
DATA
Max Load Capacitance CLOAD_SD − 30 − 30 pF
S
DATA
Pull-up Resistor RSD 1.5 4.7 1.5 4.7
kW
1. This table is based on I
2
C standard (v2.1 January 2000). Philips Semiconductor.
2. Two-wire control is I
2
C-compatible.
3. All values referred to V
IHmin
= 0.9 V
DD
_IO and V
ILmax
= 0.1 V
DD
_IO levels. Sensor EXTCLK = 27 MHz.
4. A device must internally provide a hold time of at least 300 ns for the S
DATA
signal to bridge the undefined region of the falling edge of
S
CLK
.
5. The maximum t
HD;DAT
has only to be met if the device does not stretch the LOW period (t
LOW
) of the S
CLK
signal.
6. A Fast-mode I
2
C-bus device can be used in a Standard-mode I
2
C-bus system, but the requirement t
SU;DAT
250 ns must then be met. This
will automatically be the case if the device does not stretch the LOW period of the S
CLK
signal. If such a device does stretch the LOW
period of the S
CLK
signal, it must output the next data bit to the S
DATA
line t
r
max + t
SU;DAT
= 1000 + 250 = 1250 ns (according to the Stan-
dard-mode I
2
C-bus specification) before the S
CLK
line is released.
7. Cb = total capacitance of one bus line in pF.
I/O Timing
By default, the AR0130 launches pixel data, FV and LV
with the falling edge of PIXCLK. The expectation is that the
user captures D
OUT
[11:0], FV and LV using the rising edge
of PIXCLK.
See Figure 29 and Table 9 for I/O timing (AC)
characteristics.
Figure 29. I/O Timing Diagram
EXTCLK
PIXCLK
Data[11:0]
LINE_VALID/
FRAME_VALID
Pxl_0 Pxl_1 Pxl_2 Pxl_n
t
PFL
t
PLL
t
FP
t
RP
t
F
t
R
90% 90% 90% 90%
10% 10% 10% 10%
t
EXTCLK
t
PD
t
PLH
t
PFH
FRAME_VALID Leads LINE_VALID
by 6 PIXCLKs
FRAME_VALID Trails LINE_VALID
by 6 PIXCLKs
Table 9. I/O TIMING CHARACTERISTICS (2.8 V V
DD
_IO) (Note 8)
Conditions: f
PIXCLK
= 74.25 MHz (720 P 60 fps) V
DD
_IO = 2.8 V;
Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports
Symbol Definition Condition Min Typ Max Unit
f
EXTCLK
Input Clock Frequency PLL Enabled 6 − 50 MHz
t
EXTCLK
Input Clock Period PLL Enabled 20 − 166 ns
t
R
Input Clock Rise Time − 3 − ns
t
F
Input Clock Fall Time − 3 − ns
AR0130CS
www.onsemi.com
29
Table 9. I/O TIMING CHARACTERISTICS (2.8 V V
DD
_IO) (Note 8)
Conditions: f
PIXCLK
= 74.25 MHz (720 P 60 fps) V
DD
_IO = 2.8 V;
Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports
Symbol UnitMaxTypMinConditionDefinition
Input Clock Duty Cycle 45 50 55 %
t
JITTER
(Note 9)
Input Clock Jitter at
27 MHz
− 600 − ps
t
cp
EXTCLK to PIXCLK
Propagation Delay
Nominal Voltages, PLL Disabled,
PIXCLK Slew Rate = 4
12 − 20 ns
f
PIXCLK
PIXCLK Frequency
(Note 9)
6 − 74.25 MHz
t
RP
PIXCLK Rise Time Slew Rate Setting = 4 1.60 2.70 7.50 ns
t
FP
PIXCLK Fall Time Slew Rate Setting = 4 1.50 2.60 7.20 ns
PIXCLK Duty Cycle 45 50 55 %
t
PIXJITTER
Jitter on PIXCLK − 1 − ns
t
PD
PIXCLK to Data[11:0] PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −2.5 − 3.5 ns
t
PFH
PIXCLK to FV HIGH PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −2.5 − 0.5 ns
t
PLH
PIXCLK to LV HIGH PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −3.0 − 0.0 ns
t
PFL
PIXCLK to FV LOW PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −2.5 − 0.5 ns
t
PLL
PIXCLK to LV LOW PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −3.0 − 0.0 ns
C
LOAD
Output Load
Capacitance
− 10 − pF
C
IN
Input Pin Capacitance − 2.5 − pF
8. Minimum and maximum values are for the spec limits: 3.1 V, −30°C and 2.50 V, 70°C. All values are taken at the 50% transition point.
9. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
Table 10. I/O TIMING CHARACTERISTICS (1.8 V V
DD
_IO) (Note 10)
Conditions: f
PIXCLK
= 74.25 MHz (720 P 60 fps) V
DD
_IO = 1.8 V;
Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports
Symbol Definition Condition Min Typ Max Unit
f
EXTCLK
Input Clock Frequency PLL Enabled 6 − 50 MHz
t
EXTCLK
Input Clock Period PLL Enabled 20 − 166 ns
t
R
Input Clock Rise Time − 3 − ns
t
F
Input Clock Fall Time − 3 − ns
Input Clock Duty Cycle 45 50 55 %
t
JITTER
(Note 11)
Input Clock Jitter at
27 MHz
− 600 − ps
t
cp
EXTCLK to PIXCLK
Propagation Delay
Nominal Voltages, PLL Disabled,
Slew Setting = 4
12 − 20 ns
f
PIXCLK
PIXCLK Frequency
(Note 11)
6 74.25 MHz
t
RP
Pixel Rise Time Slew Rate Setting = 4 2.50 4.30 7.10 ns
t
FP
Pixel Fall Time Slew Rate Setting = 4 2.20 3.80 6.50 ns
PIXCLK Duty Cycle PLL Enabled 45 50 55 %
t
PIXJITTER
Jitter on PIXCLK − 1 − ns
t
PD
PIXCLK to Data Valid PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −4.5 − 2.0 ns
t
PFH
PIXCLK to FV HIGH PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −4.0 − −0.5 ns
t
PLH
PIXCLK to LV HIGH PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −4.0 − −0.5 ns
10.Minimum and maximum values are are for the spec limits: 1.95 V, −30°C and 1.70 V, 70°C. All values are taken at the 50% transition point.
11. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
AR0130CS
www.onsemi.com
30
Table 10. I/O TIMING CHARACTERISTICS (1.8 V V
DD
_IO) (Note 10)
Conditions: f
PIXCLK
= 74.25 MHz (720 P 60 fps) V
DD
_IO = 1.8 V;
Slew Rate Setting = 4 for PIXCLK; Slew Rate Setting = 7 for Parallel Ports(continued)
Symbol UnitMaxTypMinConditionDefinition
t
PFL
PIXCLK to FV LOW PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −4.0 − −0.5 ns
t
PLL
PIXCLK to LV LOW PIXCLK Slew Rate = 4, Parallel Slew Rate = 7 −4.0 − −0.5 ns
C
LOAD
Output Load
Capacitance
− 10 − pF
C
IN
Input Pin Capacitance − 2.5 − pF
10.Minimum and maximum values are are for the spec limits: 1.95 V, −30°C and 1.70 V, 70°C. All values are taken at the 50% transition point.
11. Jitter from PIXCLK is already taken into account as the data of all the output parameters.
Table 11. I/O RISE SLEW RATE (2.8 V V
DD
_IO) (Note 12)
Parallel Slew (R0x306E[15:13])
Condition Min Typ Max Unit
7 Default 1.50 2.50 3.90 V/ns
6 Default 0.98 1.62 2.52 V/ns
5 Default 0.71 1.12 1.79 V/ns
4 Default 0.52 0.82 1.26 V/ns
3 Default 0.37 0.58 0.88 V/ns
2 Default 0.26 0.40 0.61 V/ns
1 Default 0.17 0.27 0.40 V/ns
0 Default 0.10 0.16 0.23 V/ns
12.Minimum and maximum values are taken at 70°C, 2.5 V and −30°C, 3.1 V. The loading used is 10 pF.
Table 12. I/O FALL SLEW RATE (2.8 V V
DD
_IO) (Note 13)
Parallel Slew (R0x306E[15:13])
Condition Min Typ Max Unit
7 Default 1.40 2.30 3.50 V/ns
6 Default 0.97 1.61 2.48 V/ns
5 Default 0.73 1.21 1.86 V/ns
4 Default 0.54 0.88 1.36 V/ns
3 Default 0.39 0.63 0.88 V/ns
2 Default 0.27 0.43 0.66 V/ns
1 Default 0.18 0.29 0.44 V/ns
0 Default 0.11 0.17 0.25 V/ns
13.Minimum and maximum values are taken at 70°C, 2.5 V and −30°C, 3.1 V. The loading used is 10 pF.
Table 13. I/O RISE SLEW RATE (1.8 V V
DD
_IO) (Note 14)
Parallel Slew (R0x306E[15:13])
Condition Min Typ Max Unit
7 Default 0.57 0.91 1.55 V/ns
6 Default 0.39 0.61 1.02 V/ns
5 Default 0.29 0.46 0.75 V/ns
4 Default 0.22 0.34 0.54 V/ns
3 Default 0.16 0.24 0.39 V/ns
2 Default 0.12 0.17 0.27 V/ns
1 Default 0.08 0.11 0.18 V/ns
0 Default 0.05 0.07 0.10 V/ns
14.Minimum and maximum values are taken at 70°C, 1.7 V and −30°C, 1.95 V. The loading used is 10 pF.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P40

AR0130CSSM00SPCAH-S115-GEVB

Mfr. #:
Buy AR0130CSSM00SPCAH-S115-GEVB
Manufacturer:
ON Semiconductor
Description:
Optical Sensor Development Tools 1.2 MP 1/3 CIS HB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet