While executing an operation, shift-in the desired operation code, followed by the
address or data bytes as listed in Table 24 on page 21. The device must drive the
nCS pin high after the last bit of the operation sequence is shifted in.
For read operations, the data read is shifted out on the DATA0 pin. You can drive the
nCS pin high when any bit of the data is shifted out.
For write and erase operations, drive the nCS pin high at a byte boundary, that is in a
multiple of eight clock pulses. Otherwise, the operation is rejected and not executed.
All attempts to access the memory contents while a write or erase cycle is in progress
are rejected, and the write or erase cycle continues unaffected.
Addressing Mode
To access the EPCQ-L256, EPCQ-L512, or EPCQ-L1024 memory, you must use the 4-
byte addressing mode. In 4-byte addressing mode, the address width is 32-bit. To
enable the 4-byte addressing mode, you must execute the 4BYTEADDREN operation.
This addressing mode takes effect immediately after you execute the 4BYTEADDREN
operation and remains active in the subsequent power-ups. To disable the 4-byte
addressing mode, you must execute the 4BYTEADDREX operation.
Note: If you are using the Intel Quartus
®
Prime software or the SRunner software to
program the EPCQ-L256, EPCQ-L512, or EPCQ-L1024 device, you do not need to
execute the 4BYTEADDREN operation. These software tools automatically enable the
4-byte addressing mode when programming the device.
Registers
Status Register
Table 14. Status Register Bits
Bit Name Value Description
7 None
6 BP3 (Block Protect
Bit)
(12)
Table 15 on page 13 through Table 20 on page 16 list the
protected area with reference to the block protect bits.
Determine the area of the
memory protected from
being written or erased
unintentionally.
5 TB (Top/Bottom Bit) • 1=Protected area starts from the bottom of the memory
array.
• 0=Protected area starts from the top of the memory
array.
Determine that the
protected area starts from
the top or bottom of the
memory array.
4 BP2
(12)
Table 15 on page 13 through Table 20 on page 16 list the
protected area with reference to the block protect bits.
Determine the area of the
memory protected from
being written or erased
unintentionally.
3 BP1
(12)
continued...
(12)
The erase bulk and erase die operation is only available when all the block protect bits are set
to 0. When any of the block protect bits are set to 1, the relevant area is protected from being
written by a write bytes operation or erased by an erase sector operation.
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
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