Write Bytes Operation (02h)
This operation allows bytes to be written to the memory. You must execute the write
enable operation before the write bytes operation. After the write bytes operation is
completed, the write enable latch bit in the status register is set to 0.
When you execute the write bytes operation, you shift in the write bytes operation
code, followed by a 4-byte addressing mode (A[31..0]), and at least one data byte
on the DATA0 pin. If the eight LSBs (A[7..0]) are not all 0, all sent data that goes
beyond the end of the current page is not written into the next page. Instead, this
data is written at the start address of the same page. You must ensure the nCS signal
is set low during the entire write bytes operation.
The following figure shows the operation sequence of the write bytes operation.
Figure 15. Write Bytes Operation Timing Diagram
DATA0
Operation Code (02h)
32-Bit Address
Data Byte 1 Data Byte 2 Data Byte 256
0
1
2
3
4
5
6
7 8 9 10 36
37
38
39
40
nCS
DCLK
41 42 43 44 45 46
47
48
49
50 51
52
53
54
55
3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 031 30 29 7 6 5 4 3 2 1 0
2072
2073
2074 2075
2076
2077
2078
2079
MSB MSB MSB MSB
If more than 256 data bytes are shifted into the EPCQ-L device with a write bytes
operation, the previously latched data is discarded and the last 256 bytes are written
to the page. However, if less than 256 data bytes are shifted into the EPCQ-L device,
they are guaranteed to be written at the specified addresses and the other bytes of
the same page are not affected.
The device initiates a self-timed write cycle immediately after the nCS signal is driven
high. For details about the self-timed write cycle time, refer to t
WB
in Table 26 on page
30. You must account for this amount of delay before another page of memory is
written. Alternatively, you can check the write in progress bit in the status register by
executing the read status operation while the self-timed write cycle is in progress. The
write in progress bit is set to 1 during the self-timed write cycle and 0 when it is
complete.
Note: You must erase all the memory bytes of EPCQ-L devices before you implement the
write bytes operation. You can erase all the memory bytes by executing the erase
sector operation in a sector or the erase bulk or erase die operation throughout the
entire memory.
Extended Quad Input Fast Write Bytes Operation (12h)
This operation is similar to the write bytes operation except that the data and
addresses are shifted in on the DATA0, DATA1, DATA2, and DATA3 pins.
The following figure shows the operation sequence of the extended quad input fast
write bytes operation.
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
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