Non-Volatile Configuration Register
Table 22. Dummy Clock Cycles and Address Bytes for the Non-Volatile Configuration
Register Operation
FPGA Device Address Bytes Dummy Clock Cycles
AS x1 AS x4
Intel Arria 10 and Intel
Cyclone 10 GX
4-byte addressing 10 10
Intel Stratix 10 4-byte addressing — 10
Table 23. Non-Volatile Configuration Register Operation Bit Definition
Bit Description Default Value
15:12 Number of dummy cycles. When this number is from 0001 to 1110, the dummy
cycles is from 1 to 14.
0000 or 1111
(15)
(16)
11:5
Set these bits to 1111111. 1111111
4 Don't care.
1
3:1
Set these bits to 111. 111
0 Address byte setting.
(17)
•
0—4-byte addressing
•
1—3-byte addressing
1
Read Non-Volatile Configuration Register Operation (B5h)
To execute a read non-volatile configuration register, drive the nCS low. For extended
SPI protocol, the operation code is input on DATA0, and output on DATA1. You can
terminate the operation by driving the nCS low at any time during data output. The
nonvolatile configuration register can be read continuously. After all 16 bits of the
register have been read, a 0 is output.
(15)
The default dummy clock cycles is 10 for extended quad input fast read and 8 for extended
dual input fast and standard fast read.
(16)
For the Intel Stratix 10 device, use the default value 1111h to set 10 dummy clock cycles.
(17)
You can only configure the Intel Arria 10 and Intel Cyclone 10 GX devices using the 4-byte
addressing mode.
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
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