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EPCQL1024F24IN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P34
Symbol Parameter Min Typical Max Unit
Erase die cycle time for EPCQ-L512
Erase die cycle time for EPCQ-L1024
t
ES
Erase sector cycle time for EPCQ-L256 — 0.7 3 s
Erase sector cycle time for EPCQ-L512
Erase sector cycle time for EPCQ-L1024
t
ESS
Erase subsector cycle time for EPCQ-L256 — 0.25 0.8 s
Erase subsector cycle time for EPCQ-L512
Erase subsector cycle time for EPCQ-L1024
Read Operation Timing
Figure 20. Read Operation Timing Diagram
DATA0
nCS
DCLK
DATA
t
nCLK2D
Add_Bit 0
Bit N Bit N - 1 Bit 0
t
CH
t
CL
t
ODIS
Table 27. Read Operation Timing Parameters
Symbol Parameter Min Max Unit
f
RCLK
Read clock frequency (from the FPGA or embedded
processor) for read bytes operations
— 50 MHz
Fast read clock frequency (from the FPGA or
embedded processor) for fast read bytes operation
— 100 MHz
t
CH
DCLK high time
4 — ns
t
CL
DCLK low time
4 — ns
t
ODIS
Output disable time after read — 8 ns
t
nCLK2D
Clock falling edge to DATA
— 7 ns
Programming and Configuration File Support
The Intel Quartus Prime software provides programming support for EPCQ-L devices.
When you select an EPCQ-L device, the Intel Quartus Prime software automatically
generates the Programmer Object File (.pof) to program the device. The software
allows you to select the appropriate EPCQ-L device density that most efficiently stores
the configuration data for the selected FPGA.
You can program the EPCQ-L device in-system by an external microprocessor using
the SRunner software driver. The SRunner software driver is developed for embedded
EPCQ-L device programming that you can customize to fit in different embedded
systems. The SRunner software driver reads .rpd files and writes to the EPCQ-L
devices. The programming time is comparable to the Intel Quartus Prime software
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
31
programming time. Because the FPGA reads the LSB of the .rpd data first during the
configuration process, the LSB of .rpd bytes must be shifted out first during the read
bytes operation and shifted in first during the write bytes operation.
Writing and reading the .rpd file to and from the EPCQ-L device is different from the
other data and address bytes.
During the ISP of an EPCQ-L device, the cable pulls the nCONFIG signal low to reset
the FPGA and overrides the 10-kΩ pull-down resistor on the nCE pin of the FPGA. The
download cable then uses the interface pins depending on the selected AS mode to
program the EPCQ-L device. When programming is complete, the download cable
releases the interface pins of the EPCQ-L device and the nCE pin of the FPGA and
pulses the nCONFIG signal to start the configuration process.
The FPGA can program the EPCQ-L device in-system using the JTAG interface with the
serial flash loader (SFL). This solution allows you to indirectly program the EPCQ-L
device using the same JTAG interface that is used to configure the FPGA.
Related Information
• Using the Serial FlashLoader with the Quartus II Software
• Altera ASMI Parallel IP Core User Guide
• Intel FPGA USB Download Cable II User Guide
• Intel FPGA USB Download Cable User Guide
• Intel FPGA Ethernet Download Cable II User Guide
• Intel FPGA Ethernet Download Cable User Guide
• Configuration, Design Security, and Remote System Upgrades in Intel Arria 10
Devices
Document Revision History for EPCQ-L Serial Configuration Devices
Datasheet
Document
Version
Changes
2018.05.18 • Updated content of Bit 3 of the Flag Status Register from VPP to Reserved.
• Updated the overshoot and undershoot note description in Absolute Maximum Ratings table.
2018.03.09 Added data retention feature information.
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
32
Date Version Changes
December 2017 2017.12.14 • Added support for Intel Cyclone 10 GX devices.
• Changed instances of the following:
— Arria 10 devices to Intel Arria 10 devices
— Stratix 10 devices to Intel Stratix 10 devices
— Quartus Prime software to Intel Quartus Prime
software
• Added operation codes for the following operations:
— Read Status Register Operation Timing Diagram
— Write Status Register Operation Timing Diagram
— Read Flag Status Register Operation Timing Diagram
— Read Non-Volatile Configuration Register Operation
Timing Diagram
— Write Non-Volatile Configuration Register Operation
Timing Diagram
— 4BYTEADDREN Timing Diagram
— 4BYTEADDREX Timing Diagram
— Write Enable Operation Timing Diagram
— Write Disable Operation Timing Diagram
— Read Bytes Operation Timing Diagram
— Fast Read Operation Timing Diagram
— Extended Quad Input Fast Read Operation Timing
Diagram
— Read Device Identification Operation Timing Diagram
— Write Bytes Operation Timing Diagram
— Extended Quad Input Fast Write Bytes Operation
Sequence
— Erase Bulk Operation Timing Diagram
— Erase Sector Operation Timing Diagram
• Updated the operation code from binary to hex for each
operation in the Operation Codes for EPCQ-L Devices
table.
• Updated the Read Flag Status Register Operation Timing
Diagram.
• Updated the note to the fast read and extended quad
input fast read operations in the Operation Codes for
EPCQ-L Devices table.
May 2017
2017.05.22 • Added Read flag status register, Dual I/O fast read, and
Extended dual input fast write bytes operations.
• Updated instances of write status operation to write
status register operation.
• Added Flag Status Register Bit Content table.
• Updated Read Status Register Operations.
• Updated Read Status Register.
December 2016 2016.12.16 • Updated address bytes for erase bulk and erase die to 4.
• Added erase subsector in Operation Codes for EPCQ-L
Devices table.
• Updated t
ESS
Max to 0.8.
October 2016 2016.10.31 • Added Stratix 10 support.
• Changed instances of Quartus II to Quartus Prime.
• Changed instances of USB-Blaster to FPGA USB
Download Cable.
• Changed instances of EthernetBlaster to FPGA Ethernet
Download Cable.
May 2016 2016.05.30 Updated Signals for EPCQ-L Devices table by replacing NC
with DNU.
continued...
EPCQ-L Serial Configuration Devices Datasheet
CF52013 | 2018.05.18
EPCQ-L Serial Configuration Devices Datasheet
33
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EPCQL1024F24IN

Mfr. #:
Buy EPCQL1024F24IN
Manufacturer:
Intel / Altera
Description:
FPGA - Configuration Memory
Lifecycle:
New from this manufacturer.
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